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S75PL127J MCPs
Stacked Multi-Chip Product (MCP) CODE Flash, pSRAM and DATA Flash 128M (8M x 16-Bit CMOS 3.0 VoltOnly, Simultaneous Operation, Page Mode CODE Flash Memory, with 64M/32M (4M/2M x 16-Bit) pSRAM and 512M/256/128M (32M/16M/8M x 16Bit) Data Flash Memory
ADVANCE INFORMATION
Data Sheet
MCP Features
Power supply voltage of 2.7 to 3.1 volt High Performance -- 65ns for PL-J, 70ns for pSRAM, and 110ns for GL-N -- Page access - 25ns
Package -- 9 x 12 mm 84 ball FBGA Operating Temperature -- -25C to +85C (Wireless) Other temperature grade options -- Please contact the factory through the local sales support team
General Description
The 75PL Series is a product line of stacked Multi-Chip Product (MCP) packages and consists of: One S29PL127J based CODE Flash device(s) pSRAM One or more S29GLxxxN based DATA Flash device(s)
32M pSRAM Code Flash Density 128M 128M S75PL127JBD
Data Flash 256M S75PL127JBE 512M S75PL127JBF
64M pSRAM Code Flash Density 128M 128M S75PL127JCD
Data Flash 256M S75PL127JCE 512M S75PL127JCF
Publication Number S75PL127J_00
Revision A
Amendment 1
Issue Date January 6, 2005
Advance
Information
S75PL127J MCPs .................................................1
General Description ...................................................1 Product Selector Guide ............................................ 5 MCP Block Diagram ................................................ 6 Connection Diagram ................................................ 7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information ............................................... 9 Valid Combinations .................................................10
Data: S29GL128N ................................................................................................ 10 Data: S29GL256N ................................................................................................ 11 Data: S29GL512N ............................................................................................... 12
Common Flash Memory Interface (CFI) ............ 40
Low VCC Write Inhibit ................................................................................ 39 Write Pulse "Glitch" Protection ............................................................... 39 Logical Inhibit ................................................................................................... 39 Power-Up Write Inhibit ............................................................................... 39
Table 9. CFI Query Identification String ................................ 40 Table 10. System Interface String ........................................ 41 Table 11. Device Geometry Definition ................................... 41 Table 12. Primary Vendor-Specific Extended Query ................ 42
Command Definitions .............................................44
Reading Array Data ...........................................................................................44 Reset Command .................................................................................................44 Autoselect Command Sequence .................................................................... 45 Enter SecSiTM Sector/Exit SecSi Sector Command Sequence ................ 45 Word Program Command Sequence ........................................................... 45 Unlock Bypass Command Sequence ........................................................46
S29PL127J/S29PL064J/S29PL032J for MCP ..... 13
General Description .................................................15
Simultaneous Read/Write Operation with Zero Latency .......................15 Page Mode Features ............................................................................................15 Standard Flash Memory Features ....................................................................15
Chip Erase Command Sequence ................................................................... 47 Sector Erase Command Sequence ................................................................48 Erase Suspend/Erase Resume Commands ..................................................49 Command Definitions Tables .........................................................................50
Figure 4. Program Operation ............................................... 47 Figure 5. Erase Operation ................................................... 49 Table 13. Memory Array Command Definitions ...................... 50 Table 14. Sector Protection Command Definitions .................. 51
Pin Description .........................................................17 Device Bus Operations ............................................18
Table 1. PL127J Device Bus Operations ................................ 18
Requirements for Reading Array Data ......................................................... 18 Random Read (Non-Page Read) ................................................................ 18 Page Mode Read .............................................................................................. 19 Simultaneous Read/Write Operation ........................................................... 19
Write Operation Status ........................................ 52
DQ7: Data# Polling ............................................................................................ 52 RY/BY#: Ready/Busy# ........................................................................................55 DQ6: Toggle Bit I ............................................................................................... 55 DQ2: Toggle Bit II .............................................................................................. 56 Reading Toggle Bits DQ6/DQ2 ..................................................................... 56 DQ5: Exceeded Timing Limits ........................................................................ 57 DQ3: Sector Erase Timer ................................................................................ 57
Figure 7. Toggle Bit Algorithm ............................................. 56 Figure 6. Data# Polling Algorithm ........................................ 54
Table 2. Page Select .......................................................... 19 Table 3. Bank Select .......................................................... 19
Writing Commands/Command Sequences ................................................ 20 Accelerated Program Operation .............................................................. 20 Autoselect Functions .................................................................................... 20 Standby Mode .......................................................................................................20 Automatic Sleep Mode ...................................................................................... 21 RESET#: Hardware Reset Pin ......................................................................... 21 Output Disable Mode ........................................................................................ 21
Table 4. PL127J Sector Architecture ..................................... 22 Table 5. SecSiTM Sector Addresses ...................................... 27 Table 6. Autoselect Codes (High Voltage Method) .................. 28 Table 7. PL127J Boot Sector/Sector Block Addresses for Protection/Unprotection ..................................................... 29 Table 8. Sector Protection Schemes ..................................... 30
Table 15. Write Operation Status ......................................... 58 Figure 8. Maximum Overshoot Waveforms ............................ 59
Absolute Maximum Ratings ...................................59 Operating Ranges ................................................... 60
Industrial (I) Devices ..........................................................................................60 Wireless Devices ................................................................................................60 Supply Voltages ...................................................................................................60
Autoselect Mode .................................................................................................27
Selecting a Sector Protection Mode ............................................................. 30
DC Characteristics .................................................. 61
Table 16. CMOS Compatible ................................................ 61
Sector Protection ................................................... 30 Sector Protection Schemes .................................. 30
Password Sector Protection ........................................................................... 30 WP# Hardware Protection ............................................................................ 30 Selecting a Sector Protection Mode ............................................................. 30 Persistent Protection Bit (PPB) ........................................................................31 Persistent Protection Bit Lock (PPB Lock) ..................................................31 Persistent Sector Protection Mode Locking Bit ........................................33 Password and Password Mode Locking Bit ................................................34 64-bit Password ...................................................................................................34 Write Protect (WP#) ........................................................................................34 Persistent Protection Bit Lock ....................................................................35 High Voltage Sector Protection ......................................................................35 Temporary Sector Unprotect .........................................................................37
AC Characteristic ....................................................62
Test Conditions .................................................................................................. 62 SWITCHING WAVEFORMS ......................................................................... 63
Figure 9. Test Setups ........................................................ 62 Table 17. Test Specifications ............................................... 62 Table 18. KEY TO SWITCHING WAVEFORMS .......................... 63 Figure 10. Input Waveforms and Measurement Levels ............ 63 Table 19. Read-Only Operations .......................................... 64 Figure 11. Read Operation Timings ...................................... 64 Figure 12. Page Read Operation Timings............................... 65 Table 20. Hardware Reset (RESET#) .................................... 65 Figure 13. Reset Timings .................................................... 66 Table 21. Erase and Program Operations .............................. 67 Figure 14. Program Operation Timings ................................. Figure 15. Accelerated Program Timing Diagram.................... Figure 16. Chip/Sector Erase Operation Timings .................... Figure 17. Back-to-back Read/Write Cycle Timings................. Figure 18. Data# Polling Timings (During Embedded Algorithms)....................................................................... Figure 19. Toggle Bit Timings (During Embedded Algorithms)....................................................................... Figure 20. DQ2 vs. DQ6 ..................................................... 68 68 69 69 70 70 71
Persistent Sector Protection ................................. 31
VCC RampRate ................................................................................................... 63 Read Operations .................................................................................................64
Password Protection Mode ................................... 33
Reset ....................................................................................................................... 65
Erase/Program Operations .............................................................................. 67 Timing Diagrams .................................................................................................68
Figure 1. In-System Sector Protection/Sector Unprotection Algorithms...................................................... 36 Figure 2. Temporary Sector Unprotect Operation .................... 37
SecSiTM (Secured Silicon) Sector Flash Memory Region ...........................37 Factory-Locked Area (64 words) ..............................................................37 Customer-Lockable Area (64 words) ......................................................38 SecSi Sector Protection Bits ........................................................................38 Hardware Data Protection ..............................................................................39
Figure 3. SecSi Sector Protect Verify..................................... 39
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27631A5 September 28, 2004
Advance
Information
Protect/Unprotect .................................................. 71
Table 22. Temporary Sector Unprotect ................................. 71 Figure 21. Temporary Sector Unprotect Timing Diagram.......... 71 Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram ................................................................. 72 Table 23. Alternate CE# Controlled Erase and Program Operations ....................................................................... 73 Table 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings ..................................................................... 74 Table 25. Erase And Programming Performance .................... 75
TM
Table 11. Primary Vendor-Specific Extended Query ............... 126
Command Definitions .......................................... 126
Reading Array Data ..........................................................................................127 Reset Command ................................................................................................127 Autoselect Command Sequence ...................................................................127 Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence ...........................................................................128 Word Program Command Sequence ..........................................................128 Unlock Bypass Command Sequence .......................................................129 Write Buffer Programming .........................................................................129 Accelerated Program ...................................................................................130 Program Suspend/Program Resume Command Sequence ...................132
Controlled Erase Operations ..........................................................................73
BGA Pin Capacitance ............................................ 75
S29GLxxxN MirrorBit
Flash Family ........... 77
Figure 1. Write Buffer Programming Operation .................... 131 Figure 2. Program Operation ............................................. 132 Figure 3. Program Suspend/Program Resume...................... 133 Figure 4. Erase Operation ................................................. 135
General Description ................................................78 Product Selector Guide ..........................................80 Block Diagram ........................................................ 81 Pin Description ....................................................... 82 Logic Symbol .......................................................... 83
S29GL512N ........................................................................................................83 S29GL256N .......................................................................................................83 S29GL128N .......................................................................................................83
Chip Erase Command Sequence .................................................................. 133 Sector Erase Command Sequence ...............................................................134
Device Bus Operations ........................................... 84
Table 1. Device Bus Operations ........................................... 84
VersatileIOTM (VIO) Control ............................................................................ 84 Requirements for Reading Array Data ........................................................ 84 Page Mode Read ............................................................................................. 85 Writing Commands/Command Sequences ................................................ 85 Write Buffer .................................................................................................... 85 Accelerated Program Operation .............................................................. 85 Autoselect Functions .................................................................................... 86 Standby Mode ...................................................................................................... 86 Automatic Sleep Mode ..................................................................................... 86 RESET#: Hardware Reset Pin ........................................................................ 86 Output Disable Mode ....................................................................................... 87
Erase Suspend/Erase Resume Commands ................................................. 135 Lock Register Command Set Definitions ...................................................136 Password Protection Command Set Definitions .....................................136 Non-Volatile Sector Protection Command Set Definitions .................138 Global Volatile Sector Protection Freeze Command Set .....................138 Volatile Sector Protection Command Set .................................................139 Secured Silicon Sector Entry Command ....................................................140 Secured Silicon Sector Exit Command .......................................................140 Command Definitions ....................................................................................... 141
Table 12. S29GL512N, S29GL256N, S29GL128N Command Definitions, x16 ................................................ 141
Write Operation Status ..................................................................................144 DQ7: Data# Polling ...........................................................................................144
RY/BY#: Ready/Busy# ......................................................................................145 DQ6: Toggle Bit I ..............................................................................................146
Figure 5. Data# Polling Algorithm ...................................... 145 Figure 6. Toggle Bit Algorithm ........................................... 147
Table 2. Sector Address Table-S29GL512N ........................... 87 Table 3. Sector Address Table-S29GL256N ..........................102 Table 4. Sector Address Table-S29GL128N ..........................109 Table 5. Autoselect Codes, (High Voltage Method) ...............114
DQ2: Toggle Bit II .............................................................................................147 Reading Toggle Bits DQ6/DQ2 ....................................................................148 DQ5: Exceeded Timing Limits .......................................................................148 DQ3: Sector Erase Timer ...............................................................................148 DQ1: Write-to-Buffer Abort ..........................................................................149
Autoselect Mode ................................................................................................ 113
Table 13. Write Operation Status ....................................... 149 Figure 7. Maximum Negative Overshoot Waveform .............. 150 Figure 8. Maximum Positive Overshoot Waveform................ 150
Sector Protection ............................................................................................... 114 Persistent Sector Protection ...................................................................... 114 Password Sector Protection ....................................................................... 114 WP# Hardware Protection ........................................................................ 114 Selecting a Sector Protection Mode ........................................................ 114 Advanced Sector Protection .......................................................................... 115 Lock Register ....................................................................................................... 115 Persistent Sector Protection .......................................................................... 116 Dynamic Protection Bit (DYB) .................................................................. 116 Persistent Protection Bit (PPB) ................................................................. 117 Persistent Protection Bit Lock (PPB Lock Bit) ..................................... 117
Absolute Maximum Ratings ................................ 150 Operating Ranges ................................................. 150 DC Characteristics ................................................. 151 Test Conditions ......................................................152
Figure 9. Test Setup ........................................................ 152 Table 14. Test Specifications ............................................. 152
Table 6. Lock Register .......................................................116
Key to Switching Waveforms .............................. 152 AC Characteristics .................................................153
Read-Only Operations-S29GL128N, S29GL256N, S29GL512N .......... 153
Figure 11. Read Operation Timings .................................... 154 Figure 12. Page Read Timings ........................................... 154 Figure 10. Input Waveforms and Measurement Levels .......... 152
Table 7. Sector Protection Schemes ....................................118
Common Flash Memory Interface (CFI) ............ 122
Persistent Protection Mode Lock Bit ..........................................................118 Password Sector Protection ........................................................................... 119 Password and Password Protection Mode Lock Bit ............................... 119 64-bit Password .................................................................................................120 Persistent Protection Bit Lock (PPB Lock Bit) .........................................120 Secured Silicon Sector Flash Memory Region ..........................................120 Write Protect (WP#) ...................................................................................... 122 Hardware Data Protection ............................................................................ 122 Low VCC Write Inhibit .............................................................................. 122 Write Pulse "Glitch" Protection .............................................................. 122 Logical Inhibit ................................................................................................. 122 Power-Up Write Inhibit .............................................................................. 122
Table 8. CFI Query Identification String............................... 123 Table 9. System Interface String ........................................ 124 Table 10. Device Geometry Definition ................................. 125
Hardware Reset (RESET#) ............................................................................. 155 Erase and Program Operations-S29GL128N, S29GL256N, S29GL512N ..........................................................................................................156
Figure 14. Program Operation Timings ............................... Figure 15. Accelerated Program Timing Diagram.................. Figure 16. Chip/Sector Erase Operation Timings .................. Figure 17. Data# Polling Timings (During Embedded Algorithms)..................................................................... Figure 18. Toggle Bit Timings (During Embedded Algorithms) Figure 19. DQ2 vs. DQ6 ................................................... Figure 13. Reset Timings .................................................. 155
157 157 158 159 160 160
Alternate CE# Controlled Erase and Program OperationsS29GL128N, S29GL256N, S29GL512N .........................................................161
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Information
Erase And Programming Performance .............. 163 TSOP Pin and BGA Package Capacitance ......... 163
Figure 20. Alternate CE# Controlled Write (Erase/ Program) Operation Timings .............................................. 162
pSRAM Type 2 ................................................164
Features ................................................................ 164 Product Information ............................................ 164 Pin Description ..................................................... 164 Power Up Sequence ............................................. 165 Timing Diagrams ...................................................166
Power Up ............................................................................................................ 166
Figure 21. Power Up 1 (CS1# Controlled) ............................ 166 Figure 22. Power Up 2 (CS2 Controlled) .............................. 166
pSRAM Type 6 ................................................174
Features ................................................................. Pin Description ..................................................... Functional Description ......................................... Absolute Maximum Ratings ................................ DC Recommended Operating Conditions (Ta = -40C to 85C) ............................................. DC Characteristics (Ta = -40C to 85C, VDD = 2.6 to 3.3 V) (See Note 3 to 4) ................ Capacitance (Ta = 25C, f = 1 MHz) .................... AC Characteristics and Operating Conditions .............................................................
Figure 29. Timing Waveform of Write Cycle(3) (CS2 Controlled) ............................................................. 173 Figure 30. Timing Waveform of Write Cycle(4) (UB#, LB# Controlled) ..................................................................... 173
174 174 175 175 175 176 176 176
Functional Description ........................................ 166 Absolute Maximum Ratings ................................. 167 DC Recommended Operating Conditions ......... 167 Capacitance (Ta = 25C, f = 1 MHz) .................... 167 DC and Operating Characteristics ..................... 167
AC Operating Conditions ................................... 169
Common .............................................................................................................. 167 16M pSRAM .........................................................................................................168 32M pSRAM ........................................................................................................168 64M pSRAM ........................................................................................................ 169 Test Conditions (Test Load and Test Input/Output Reference) ....... 169 ACC Characteristics (Ta = -40C to 85C, VCC = 2.7 to 3.1 V) ........ 170
Figure 23. Output Load ..................................................... 169
AC Test Conditions .............................................. 177 Timing Diagrams ................................................... 178
Read Timings .......................................................................................................178 Write Timings .................................................................................................... 180
Figure 1. Read Cycle ........................................................ 178 Figure 2. Page Read Cycle (8 Words Access) ....................... 179 Figure 3. Write Cycle #1 (WE# Controlled) (See Note 8) ...... 180 Figure 4. Write Cycle #2 (CE# Controlled) (See Note 8) ....... 181 Figure 5. Deep Power Down Timing.................................... 181 Figure 6. Power-on Timing ................................................ 181 Figure 7. Read ................................................................ 182
(Ta = -40C to 85C, VDD = 2.6 to 3.3 V) (See Note 5 to 11) ............176
Timing Diagrams ....................................................171
Read Timings ....................................................................................................... 171
Figure 24. Timing Waveform of Read Cycle(1)...................... 171 Figure 25. Timing Waveform of Read Cycle(2)...................... 171 Figure 26. Timing Waveform of Read Cycle(2)...................... 171 Figure 27. Write Cycle #1 (WE# Controlled) ........................ 172 Figure 28. Write Cycle #2 (CS1# Controlled) ....................... 172
Deep Power-down Timing ..............................................................................181
Power-on Timing ................................................................................................181 Provisions of Address Skew ...........................................................................182 Read ...................................................................................................................182 Write .................................................................................................................182
Write Timings .................................................................................................... 172
Revision Summary .........................................183
Figure 8. Write ................................................................ 182
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27631A5 September 28, 2004
Prelimiary
Product Selector Guide
PL127J Access Times (ns) pSRAM Data pSRAM Access Storage density Time (ns) Supplier Density 32 Mb 65 64 Mb 70 Type 6 Type 2 Type 6 Type 2 Type 6 70 64 Mb Type 2 Type 6 Type 2 Type 6 70 64 Mb Type 2 Type 6 Type 2 512 Mb (110ns) 9x12 mm 84-ball FBGA 256 Mb (110ns) 9x12 mm 84-ball FBGA 128 Mb (110ns) 9x12 mm 84-ball FBGA
Device-Model# S75PL127JBD-KU S75PL127JBD-KB S75PL127JCD-KU S75PL127JCD-KB S75PL127JBE-KU S75PL127JBE-KB S75PL127JCE-KU S75PL127JCE-KB S75PL127JBF-KU S75PL127JBF-KB S75PL127JCF-KU S75PL127JCF-KB
Package
32 Mb 65
32 Mb 65
January 6, 2005 S75PL127J_00_A1_E
S75PL127J MCPs
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Advance
Information
MCP Block Diagram
VCCf Amax*-A22 23 Shared Address WP#ACC F1-CE# (See Note) OE# WE# F-RST# F2-CW# (See Note) WP# CE# OE# WE# RESET# VSS VSS RDY S29GL-N RY/BY# S29PL127J DQ15 to DQ0
Flash-Only Address
VCCf 16 DQ15 to DQ0
R-VCC
VCC 23
VCCO 16 DQ15 to DQ0
R-CE#
CE# WE# OE# pSRAM
R-UB# R-LB# (Note 1) R-CE2
UB# LB#
VSSQ VSS
Note: F1-CE# and F2-CE# are the chip-enable pins for the PL and GL Flash devices, respectively.
Amax -A24 for GL512, A23 for GL256N, A22 for GL128 and PL127J. Flash-only addressess may be shared between PL and GL, but is not shared with pSRAM. For more details, refer to the table following the connection diagram.
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S75PL127J MCPs
S75PL127J_00_A1_E January 6, 2005
Prelimiary
Connection Diagram
Legend: Top View A1 DNU B2 RFU C2 RFU D2 A3 E2 A2 F2 A1 G2 A0 H2 F1-CE# J2 R-CE1# K2 RFU L2 RFU B3 VSS C3 A7 D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K4 DQ8 L3 RFU B4 RFU C4 B5 RFU C5 B6 F-VCC C6 WE# D6 R-CE2 E6 A20 F6 A23 G6 RFU H6 DQ4 J6 R-VCC K6 RFU L6 RFU B7 RFU C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 L7 RFU B8 RFU C8 A11 D8 A12 E8 A13 F8 A14 G8 A24 H8 DQ15 J8 DQ7 K8 B9 RFU C9 F2-CE# D9 A15 Reserved for Future Use E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 L4 VSS E5 RY/BY# F5 RFU G5 RFU H5 DQ3 J5 F-VCC K5 DQ11 L5 F-VCC E9 A21 F9 A22 G9 A16 H9 RFU J9 VSS K9 Shared (See Table Below) PL and GL Shared PL (Code) Only pSRAM only GL (Data) only A2 DNU All Shared
R-LB# F1-WP/ACC D4 R-UB# D5 F-RST#
DQ14 F2-WP#/ACC L8 RFU L9 RFU
DNU
DNU
Note: Connect 2-WP#/ ACC (K9) to Flash Vcc.
MCP S75PL127JBD S75PL127JCD S75PL127JBE S75PL127JCE S75PL127JBF S75PL127JCF
GL-Only Addresses PL-GL Shared Addresses A23 A23 A24-A23 A24-A23 A22-A21 A22 A22-A21 A22 A22-A21 A22
PL, GL, and pSRAM Shared Addresses A20-A0 A21-A0 A20-A0 A21-A0 A20-A0 A21-A0
January 6, 2005 S75PL127J_00_A1_E
S75PL127J MCPs
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Advance
Information
Pin Description
Amax-A0 DQ15-DQ0 F1-CE# F2-CE = Address Inputs = 16 Data Inputs/Outputs (Common) = Chip Enable for PL = Chip Enable for GL = R-CE#1 R-CE#2 OE# WE# RY/BY# R-UB# R-LB# F-RST# F1-WP#/ACC F-VCC R-VCCs VSS DNU = Chip Enable 1 (pSRAM) = Chip Enable 2 (pSRAM) = Output Enable (Common) = Write Enable (Common) = Ready/Busy Output (Flash) = Upper Byte Control (pSRAM) = Lower Byte Control (pSRAM) = Hardware Reset Pin (Flash) = Hardware Write Protect /Acceleration Pin (PL) Hardware Write Protect/Acceleration Pin (GL) Should be tied to Vcc = Flash 3.0 volt-only single power supply = pSRAM Power Supply = Device Ground (Common) = Do Not Use
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S75PL127J MCPs
S75PL127J_00_A1_E January 6, 2005
Prelimiary
Ordering Information
S75PL 127 J C D BA W K Z 0
PACKING TYPE 0 = Tray 2 = 7" Tape and Reel 3 = 13" Tape and Reel SUPPPLIER; SPEED COMBINATION B = pSRAM2, 70 ns U = pSRAM6, 70 ns PACKAGE HEIGHT; DATA TYPE; PSRAM SPEED K = 1.4 mm, GL as data; 70 ns TEMPERATURE RANGE W = Wireless (-25C to +85C) PACKAGE TYPE BA = Very Thin Fine-Pitch BGA Lead (Pb)-free compliant package BF = Very Thin Fine-Pitch BGA Lead (Pb)-free package GL DATA Flash Density D = 128 Mb E = 256 Mb F = 512 Mb pSRAM Density B = 32 Mb C = 64 Mb PROCESS TECHNOLOGY J = 110 nm, Floating Gate PL CODE FLASH DENSITY 127 = 128 Mb PRODUCT FAMILY S75PL = Multi-Chip Product (MCP) 3.0 V Simultaneous Read/Write Page Mode CODE Flash + pSRAM + 3.0V DATA Flash
January 6, 2005 S75PL127J_00_A1_E
S75PL127J MCPs
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Information
Valid Combinations
Data: S29GL128N
Package Package Base Ordering & Modifier/ Part Number Temperature Model Number S75PL127JBD S75PL127JBD S75PL127JCD S75PL127JCD S75PL127JBD S75PL127JBD S75PL127JCD S75PL127JCD BFW BAW KU KB KU KB KU KB KU KB 0, 2, 3, (Note 1) 65 Packing Type PL127J Speed Options pSRAM Supplier/ Package Access Time (ns) Marking (ns) Type 6 / 70 Type 2 / 70 Type 6/ 70 Type 2 / 70 Type 6 / 70 Type 2 / 70 Type 6 / 70 Type 2 / 70 (Note 2)
Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading S and packing type designator from ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Data: S29GL256N
Package Package Base Ordering & Modifier/ Part Number Temperature Model Number S75PL127JBE S75PL127JBE S75PL127JCE S75PL127JCE S75PL127JBE S75PL127JBE S75PL127JCE S75PL127JCE BFW BAW KU KB KU KB KU KB KU KB 0, 2, 3, (Note 1) 65 PL127J Speed Packing Options pSRAM Supplier/ Package Type Access Time (ns) Marking (ns) Type 6 / 70 Type 2 / 70 Type 6 / 70 Type 2 / 70 Type 6 / 70 Type 2 / 70 Type 6 / 70 Type 2 / 70 (Note 2)
Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading S and packing type designator from ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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S75PL127J MCPs
S75PL127J_00_A1_E January 6, 2005
Prelimiary
Data: S29GL512N
Package Package Base Ordering Packing & Modifier/ Part Number Temperature Model Number Type S75PL127JBF S75PL127JBF S75PL127JCF S75PL127JCF S75PL127JBF S75PL127JBF S75PL127JCF S75PL127JCF BFW BAW KU KB KU KB KU KB KU KB 0, 2, 3, (Note 1) 65 PL127J Speed Options pSRAM Supplier/ Package Access Time (ns) Marking (ns) Type 6 / 70 Type 2 / 70 Type 6 / 70 Type 2 / 70 Type 6 / 70 Type 2 / 70 Type 6 / 70 Type 2 / 70 (Note 2)
Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading S and packing type designator from ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
January 6, 2005 S75PL127J_00_A1_E
S75PL127J MCPs
11
S29PL127J/S29PL064J/S29PL032J for MCP
128/64/32 Megabit (8/4/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIOTM Control
PRELIMINARY
Distinctive Characteristics
ARCHITECTURAL ADVANTAGES
128/64/32 Mbit Page Mode devices -- Page size of 8 words: Fast page read access from random locations within the page Single power supply operation -- Full Voltage range: 2.7 to 3.1 volt read, erase, and program operations for battery-powered applications Simultaneous Read/Write Operation -- Data can be continuously read from one bank while executing erase/program functions in another bank -- Zero latency switching from write to read operations FlexBank Architecture (PL127J/PL064J/PL032J) -- 4 separate banks, with up to two simultaneous operations per device -- Bank A: PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31) PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15) PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7) -- Bank B: PL127J - 48 Mbit (32 Kw x 96) PL064J - 24 Mbit (32 Kw x 48) PL032J - 12 Mbit (32 Kw x 24) -- Bank C: PL127J - 48 Mbit (32 Kw x 96) PL064J - 24 Mbit (32 Kw x 48) PL032J - 12 Mbit (32 Kw x 24) -- Bank D: PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31) PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15) PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7) Enhanced VersatileI/OTM (VIO) Control -- Output voltage generated and input voltages tolerated on all control inputs and I/Os is determined by the voltage on the VIO pin -- VIO options at 1.8 V and 3 V I/O for PL127J devices -- 3V VIO for PL064J and PL032J devices SecSiTM (Secured Silicon) Sector region -- Up to 128 words accessible through a command sequence -- Up to 64 factory-locked words -- Up to 64 customer-lockable words Both top and bottom boot blocks in one device Manufactured on 110 nm process technology Data Retention: 20 years typical Cycling Endurance: 1 million cycles per sector typical
PERFORMANCE CHARACTERISTICS
High Performance -- Page access times as fast as 20 ns -- Random access times as fast as 55 ns Power consumption (typical values at 10 MHz) -- 45 mA active read current -- 17 mA program/erase current -- 0.2 A typical standby mode current
SOFTWARE FEATURES
Software command-set compatible with JEDEC 42.4 standard -- Backward compatible with Am29F, Am29LV, Am29DL, and AM29PDL families and MBM29QM/RM, MBM29LV, MBM29DL, MBM29PDL families CFI (Common Flash Interface) compliant -- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices Erase Suspend / Erase Resume -- Suspends an erase operation to allow read or program operations in other sectors of same bank Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences
Publication Number S29PL127J_064J_032J_MCP
Revision A
Amendment 3
Issue Date August 12, 2004
Preliminary
HARDWARE FEATURES
Ready/Busy# pin (RY/BY#) -- Provides a hardware method of detecting program or erase cycle completion Hardware reset pin (RESET#) -- Hardware method to reset the device to reading array data WP#/ ACC (Write Protect/Acceleration) input -- At VIL, hardware level protection for the first and last two 4K word sectors. -- At VIH, allows removal of sector protection -- At VHH, provides accelerated programming in a factory setting Persistent Sector Protection -- A command sector protection method to lock combinations of individual sectors and sector groups
to prevent program or erase operations within that sector -- Sectors can be locked and unlocked in-system at VCC level Password Sector Protection -- A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password Package options -- Standard discrete pinouts 11 x 8 mm, 80-ball Fine-pitch BGA (PL127J) (VBG080) 8 x 6 mm, 48-ball Fine pitch BGA (PL064J/PL032J) (VBK048) -- MCP-compatible pinout 8 x 11.6 mm, 64-ball Fine-pitch BGA (PL127J) 7 x 9 mm, 56-ball Fine-pitch BGA (PL064J and PL032J) Compatible with MCP pinout, allowing easy integration of RAM into existing designs
14
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
General Description
The PL127J/PL064J/PL032J is a 128/128/64/32 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8/8/4/2 Mwords. The devices are offered in the following packages: 11mm x 8mm, 64-ball Fine-pitch BGA standalone (all) 9mm x 8mm, 80-ball Fine-pitch BGA standalone (PL127J) 8mm x 11.6mm, 64-ball Fine pitch BGA multi-chip compatible (PL127J) The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations. The device offers fast page access times of 20 to 30 ns, with corresponding random access times of 55 to 70 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Simultaneous Read/Write Operation with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows: Bank A B C D PL127J Sectors 16 Mbit (4 Kw x 8 and 32 Kw x 31) 48 Mbit (32 Kw x 96) 48 Mbit (32 Kw x 96) 16 Mbit (4 Kw x 8 and 32 Kw x 31)
Page Mode Features
The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 singlepower-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry.
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
15
Preliminary
Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. The device electrically erases all bits within a sector simultaneously via FowlerNordheim tunneling. The data is programmed using hot electron injection.
16
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
Pin Description
Amax-A0 DQ15-DQ0 CE# OE# WE# VSS NC RY/BY# = = = = = = = = Address bus 16-bit data inputs/outputs/float Chip Enable Inputs Output Enable Input Write Enable Device Ground Pin Not Connected Internally Ready/Busy output and open drain. When RY/BY#= VIH, the device is ready to accept read operations and commands. When RY/BY#= VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation. Write Protect/Acceleration Input. When WP#/ACC= VIL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP#/ ACC= VIH, these sector are unprotected unless the DYB or PPB is programmed. When WP#/ACC= 12V, program and erase operations are accelerated. Input/Output Buffer Power Supply (1.65 V to 1.95 V (for PL127J) or 2.7 V to 3.6 V (for all PLxxxJ devices) Chip Power Supply (2.7 V to 3.6 V or 2.7 to 3.3 V) Hardware Reset Pin Chip Enable Inputs
WP#/ACC
=
VIO VCC RESET# CE#1
=
= = =
Notes: 1. Amax = A22 (PL127J), A21 (PL064J), A20 (PL032J)
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
17
Preliminary
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Table 1. PL127J Device Bus Operations
Operation Read Write Standby Output Disable Reset Temporary Sector Unprotect (High Voltage) CE# L L VIO 0.3 V L X X OE# L H X H X X WE# H L X H X X RESET# H H VIO 0.3 V H L VID WP#/ACC X X (Note 2) X (Note 2) X X X Addresses (Amax-A0) AIN AIN X X X AIN DQ15- DQ0 DOUT DIN High-Z High-Z High-Z DIN
Legend: L= Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 8.5-9.5 V, X = Don't Care,
SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes: 1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the High Voltage Sector Protection section. 2. WP#/ACC must be high when writing to upper two and lower two sectors.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the OE# and appropriate CE# pins. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to Table 19 for timing specifications and to Figure 11 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data.
Random Read (Non-Page Read)
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The output enable access time is the delay from the falling edge of the OE# to valid data at the output inputs (assuming the addresses have been stable for at least tACC-tOE time).
18
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. Address bits Amax-A3 select an 8 word page, and address bits A2-A0 select a specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. The random or initial page access is tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. Fast page mode accesses are obtained by keeping Amax-A3 constant and changing A2-A0 to select the specific word within that page.
Table 2.
Word Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7
Page Select
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1
Simultaneous Read/Write Operation
In addition to the conventional features (read, program, erase-suspend read, and erase-suspend program), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation). The bank can be selected by bank addresses (PL127J: A22-A20, L064J: A21-A19, PL032J: A20-A18) with zero latency. The simultaneous operation can execute multi-function mode in the same bank.
Table 3.
Bank Select PL127J: A22-A20 PL064J: A21-A19 PL032J: A20-A18
000 001, 010, 011 100, 101, 110 111
Bank Bank A Bank B Bank C Bank D
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
19
Preliminary
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The "Word Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 4 indicates the set of address space that each sector occupies. A "bank address" is the set of address bits required to uniquely select a bank. Similarly, a "sector address" refers to the address bits required to uniquely select a sector. The "Command Definitions" section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. ICC2 in the DC Characteristics table represents the active current specification for the write mode. See the timing specification tables and timing diagrams in the Reset for write operations.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin should be raised to VCC when not in use. That is, the WP#/ACC pin should not be left floating or unconnected; inconsistent behavior of the device may result.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15-DQ0. Standard read cycle timings apply in this mode. Refer to the SecSiTM Sector Addresses and Autoselect Command Sequence for more information.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VIO 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device
20
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in "DC Characteristics" represents the CMOS standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during automatic sleep mode, OE# must be at VIH before the device reduces current to the stated sleep mode specification. ICC5 in "DC Characteristics" represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/ BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristic tables for RESET# parameters and to 13 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are placed in the highest Impedance state
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
21
Preliminary
Table 4. PL127J Sector Architecture
Bank Sector
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 Bank A SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
Sector Address (A22-A12)
00000000000 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 00000001XXX 00000010XXX 00000011XXX 00000100XXX 00000101XXX 00000110XXX 00000111XXX 00001000XXX 00001001XXX 00001010XXX 00001011XXX 00001100XXX 00001101XXX 00001110XXX 00001111XXX 00010000XXX 00010001XXX 00010010XXX 00010011XXX 00010100XXX 00010101XXX 00010110XXX 00010111XXX 00011000XXX 00011001XXX 00011010XXX 00011011XXX 00011100XXX 00011101XXX 00011110XXX 00011111XXX
Sector Size (Kwords)
4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Address Range (x16)
000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
Table 4.
Bank Sector
SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 Bank B SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78
PL127J Sector Architecture (Continued)
Sector Address (A22-A12)
00100000XXX 00100001XXX 00100010XXX 00100011XXX 00100100XXX 00100101XXX 00100110XXX 00100111XXX 00101000XXX 00101001XXX 00101010XXX 00101011XXX 00101100XXX 00101101XXX 00101110XXX 00101111XXX 00110000XXX 00110001XXX 00110010XXX 00110011XXX 00110100XXX 00110101XXX 00110110XXX 00110111XXX 00111000XXX 00111001XXX 00111010XXX 00111011XXX 00111100XXX 00111101XXX 00111110XXX 00111111XXX 01000000XXX 01000001XXX 01000010XXX 01000011XXX 01000100XXX 01000101XXX 01000110XXX 01000111XXX
Sector Size (Kwords)
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Address Range (x16)
100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
23
Preliminary
Table 4.
Bank Sector
SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 Bank B SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118
PL127J Sector Architecture (Continued)
Sector Address (A22-A12)
01001000XXX 01001001XXX 01001010XXX 01001011XXX 01001100XXX 01001101XXX 01001110XXX 01001111XXX 01010000XXX 01010001XXX 01010010XXX 01010011XXX 01010100XXX 01010101XXX 01010110XXX 01010111XXX 01011000XXX 01011001XXX 01011010XXX 01011011XXX 01011100XXX 01011101XXX 01011110XXX 01011111XXX 01100000XXX 01100001XXX 01100010XXX 01100011XXX 01100100XXX 01100101XXX 01100110XXX 01100111XXX 01101000XXX 01101001XXX 01101010XXX 01101011XXX 01101100XXX 01101101XXX 01101110XXX 01101111XXX
Sector Size (Kwords)
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Address Range (x16)
240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh
24
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
Table 4.
Bank Sector
SA119 SA120 SA121 SA122 SA123 SA124 SA125 Bank B SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 Bank C SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158
PL127J Sector Architecture (Continued)
Sector Address (A22-A12)
01110000XXX 01110001XXX 01110010XXX 01110011XXX 01110100XXX 01110101XXX 01110110XXX 01110111XXX 01111000XXX 01111001XXX 01111010XXX 01111011XXX 01111100XXX 01111101XXX 01111110XXX 01111111XXX 10000000XXX 10000001XXX 10000010XXX 10000011XXX 10000100XXX 10000101XXX 10000110XXX 10000111XXX 10001000XXX 10001001XXX 10001010XXX 10001011XXX 10001100XXX 10001101XXX 10001110XXX 10001111XXX 10010000XXX 10010001XXX 10010010XXX 10010011XXX 10010100XXX 10010101XXX 10010110XXX 10010111XXX
Sector Size (Kwords)
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Address Range (x16)
380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh 400000h-407FFFh 408000h-40FFFFh 410000h-417FFFh 418000h-41FFFFh 420000h-427FFFh 428000h-42FFFFh 430000h-437FFFh 438000h-43FFFFh 440000h-447FFFh 448000h-44FFFFh 450000h-457FFFh 458000h-45FFFFh 460000h-467FFFh 468000h-46FFFFh 470000h-477FFFh 478000h-47FFFFh 480000h-487FFFh 488000h-48FFFFh 490000h-497FFFh 498000h-49FFFFh 4A0000h-4A7FFFh 4A8000h-4AFFFFh 4B0000h-4B7FFFh 4B8000h-4BFFFFh
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
25
Preliminary
Table 4.
Bank Sector
SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 Bank C SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198
PL127J Sector Architecture (Continued)
Sector Address (A22-A12)
10011000XXX 10011001XXX 10011010XXX 10011011XXX 10011100XXX 10011101XXX 10011110XXX 10011111XXX 10100000XXX 10100001XXX 10100010XXX 10100011XXX 10100100XXX 10100101XXX 10100110XXX 10100111XXX 10101000XXX 10101001XXX 10101010XXX 10101011XXX 10101100XXX 10101101XXX 10101110XXX 10101111XXX 10110000XXX 10110001XXX 10110010XXX 10110011XXX 10110100XXX 10110101XXX 10110110XXX 10110111XXX 10111000XXX 10111001XXX 10111010XXX 10111011XXX 10111100XXX 10111101XXX 10111110XXX 10111111XXX
Sector Size (Kwords)
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Address Range (x16)
4C0000h-4C7FFFh 4C8000h-4CFFFFh 4D0000h-4D7FFFh 4D8000h-4DFFFFh 4E0000h-4E7FFFh 4E8000h-4EFFFFh 4F0000h-4F7FFFh 4F8000h-4FFFFFh 500000h-507FFFh 508000h-50FFFFh 510000h-517FFFh 518000h-51FFFFh 520000h-527FFFh 528000h-52FFFFh 530000h-537FFFh 538000h-53FFFFh 540000h-547FFFh 548000h-54FFFFh 550000h-557FFFh 558000h-15FFFFh 560000h-567FFFh 568000h-56FFFFh 570000h-577FFFh 578000h-57FFFFh 580000h-587FFFh 588000h-58FFFFh 590000h-597FFFh 598000h-59FFFFh 5A0000h-5A7FFFh 5A8000h-5AFFFFh 5B0000h-5B7FFFh 5B8000h-5BFFFFh 5C0000h-5C7FFFh 5C8000h-5CFFFFh 5D0000h-5D7FFFh 5D8000h-5DFFFFh 5E0000h-5E7FFFh 5E8000h-5EFFFFh 5F0000h-5F7FFFh 5F8000h-5FFFFFh
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
Table 4.
Bank Sector
SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 Bank C SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230
PL127J Sector Architecture (Continued)
Sector Address (A22-A12)
11000000XXX 11000001XXX 11000010XXX 11000011XXX 11000100XXX 11000101XXX 11000110XXX 11000111XXX 11001000XXX 11001001XXX 11001010XXX 11001011XXX 11001100XXX 11001101XXX 11001110XXX 11001111XXX 11010000XXX 11010001XXX 11010010XXX 11010011XXX 11010100XXX 11010101XXX 11010110XXX 11010111XXX 11011000XXX 11011001XXX 11011010XXX 11011011XXX 11011100XXX 11011101XXX 11011110XXX 11011111XXX
Sector Size (Kwords)
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Address Range (x16)
600000h-607FFFh 608000h-60FFFFh 610000h-617FFFh 618000h-61FFFFh 620000h-627FFFh 628000h-62FFFFh 630000h-637FFFh 638000h-63FFFFh 640000h-647FFFh 648000h-64FFFFh 650000h-657FFFh 658000h-65FFFFh 660000h-667FFFh 668000h-66FFFFh 670000h-677FFFh 678000h-67FFFFh 680000h-687FFFh 688000h-68FFFFh 690000h-697FFFh 698000h-69FFFFh 6A0000h-6A7FFFh 6A8000h-6AFFFFh 6B0000h-6B7FFFh 6B8000h-6BFFFFh 6C0000h-6C7FFFh 6C8000h-6CFFFFh 6D0000h-6D7FFFh 6D8000h-6DFFFFh 6E0000h-6E7FFFh 6E8000h-6EFFFFh 6F0000h-6F7FFFh 6F8000h-6FFFFFh
Table 5.
SecSiTM Sector Addresses
Sector Size Address Range 000000h-00003Fh 000040h-00007Fh
Factory-Locked Area Customer-Lockable Area
64 words 64 words
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device
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Preliminary
to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be set as shown in Table 6. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 3). Table 6 shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. However, the autoselect codes can also be accessed in-system through the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 13. Note that if a Bank Address (BA) (on address bits PL127J: A22-A20, PL064J: A21-A19, PL032J: A20-A18) is asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 13. This method does not require V ID . Refer to the Autoselect Command Sequence for more information.
Table 6. Autoselect Codes (High Voltage Method)
Description Manufacturer ID: Spansion products Read Cycle 1 Device ID Read Cycle 2 Read Cycle 3 Sector Protection Verification SecSi Indicator Bit (DQ7, DQ6) CE# OE# WE# Amax to A12 BA A1 0 A9 A8 A7 A6 A5 to A4 X A3 A2 A1 A0 DQ15 to DQ0
L
L
H
X
VID
X
L
L
L
L
L
L
0001h
L
L
L
L
H
227Eh 2220h (PL127J) 2202h (PL064J) 220Ah (PL032J) 2200h (PL127J) 2201h (PL064J) 2201h (PL032J) 0001h (protected), 0000h (unprotected) 00C4h (factory and customer locked), 0084h (factory locked), 0004h (not locked)
L
L
H
BA
X
VID
X
L
L
L
H
H
H
L
L
H
H
H
H
L
L
H
SA
X
VID
X
L
L
L
L
L
H
L
L
L
H
BA
X
VID
X
X
L
X
L
L
H
H
Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don't care. Note: The autoselect codes may also be accessed in-system via command sequences
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S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
Table 7.
Sector
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11-SA14 SA15-SA18 SA19-SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55-SA58 SA59-SA62 SA63-SA66 SA67-SA70 SA71-SA74 SA75-SA78 SA79-SA82 SA83-SA86 SA87-SA90 SA91-SA94 SA95-SA98 SA99-SA102 SA103-SA106 SA107-SA110 SA111-SA114 SA115-SA118 SA119-SA122 SA123-SA126 SA127-SA130
PL127J Boot Sector/Sector Block Addresses for Protection/Unprotection
A22-A12
00000000000 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 00000001XXX 00000010XXX 00000011XXX 000001XXXXX 000010XXXXX 000011XXXXX 000100XXXXX 000101XXXXX 000110XXXXX 000111XXXXX 001000XXXXX 001001XXXXX 001010XXXXX 001011XXXXX 001100XXXXX 001101XXXXX 001110XXXXX 001111XXXXX 010000XXXXX 010001XXXXX 010010XXXXX 010011XXXXX 010100XXXXX 010101XXXXX 010110XXXXX 010111XXXXX 011000XXXXX 011001XXXXX 011010XXXXX 011011XXXXX 011100XXXXX 011101XXXXX 011110XXXXX
Sector/ Sector Block Size
4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords
Sector
SA131-SA134 SA135-SA138 SA139-SA142 SA143-SA146 SA147-SA150 SA151-SA154 SA155-SA158 SA159-SA162 SA163-SA166 SA167-SA170 SA171-SA174 SA175-SA178 SA179-SA182 SA183-SA186 SA187-SA190 SA191-SA194 SA195-SA198 SA199-SA202 SA203-SA206 SA207-SA210 SA211-SA214 SA215-SA218 SA219-SA222 SA223-SA226 SA227-SA230 SA231-SA234 SA235-SA238 SA239-SA242 SA243-SA246 SA247-SA250 SA251-SA254 SA255-SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265
A22-A12
011111XXXXX 100000XXXXX 100001XXXXX 100010XXXXX 100011XXXXX 100100XXXXX 100101XXXXX 100110XXXXX 100111XXXXX 101000XXXXX 101001XXXXX 101010XXXXX 101011XXXXX 101100XXXXX 101101XXXXX 101110XXXXX 101111XXXXX 110000XXXXX 110001XXXXX 110010XXXXX 110011XXXXX 110100XXXXX 110101XXXXX 110110XXXXX 110111XXXXX 111000XXXXX 111001XXXXX 111010XXXXX 111011XXXXX 111100XXXXX 111101XXXXX 111110XXXXX 11111100XXX 11111101XXX 11111110XXX 11111111000 11111111001 11111111010 11111111011
Sector/ Sector Block Size
128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords
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Preliminary
Selecting a Sector Protection Mode
The device is shipped with all sectors unprotected. Optional Spansion programming services enable programming and protecting sectors at the factory prior to shipping the device. Contact your local sales office for details. It is possible to determine whether a sector is protected or unprotected. See the SecSiTM Sector Addresses for details.
Table 8. Sector Protection Schemes
DYB 0 0 0 1 1 0 1 1 PPB 0 0 1 0 1 1 0 1 PPB Lock 0 1 0 0 0 1 1 1 Protected--PPB not changeable, DYB is changeable Protected--PPB and DYB are changeable Sector State Unprotected--PPB and DYB are changeable Unprotected--PPB not changeable, DYB is changeable
Sector Protection
The PL127J, PL064J, and PL032J features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups.
Sector Protection Schemes
Password Sector Protection
A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted
WP# Hardware Protection
A write protect pin that can prevent program or erase operations in sectors SA1133, SA1-134, SA2-0 and SA2-1. The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen.
Selecting a Sector Protection Mode
All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. If the Persistent Sector Protection method is desired, programming the Persistent Sector Protection Mode Locking Bit permanently sets the device to the Persistent Sector Protection mode. If the Password Sector Protection method is desired, programming the Password Mode Locking Bit permanently sets the device to the Password Sector Protection mode. It is not possible to switch between the two protection modes once a locking bit has been set. One of the two modes must be selected when the device is first programmed. This prevents a program or virus from later setting the Password
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The device is shipped with all sectors unprotected. Optional Spansion programming services enable programming and protecting sectors at the factory prior to shipping the device. Contact your local sales office for details. It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode for details.
Persistent Sector Protection
The Persistent Sector Protection method replaces the 12 V controlled protection method in previous flash devices. This new method provides three different sector protection states: Persistently Locked--The sector is protected and cannot be changed. Dynamically Locked--The sector is protected and can be changed by a simple command. Unlocked--The sector is unprotected and can be changed by a simple command. To achieve these states, three types of "bits" are used: Persistent Protection Bit Persistent Protection Bit Lock Persistent Sector Protection Mode Locking Bit
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). All 4 Kword boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Otherwise, a previously erased sector PPBs can potentially be over-erased. The flash device does not have a built-in means of preventing sector PPBs over-erasure.
Persistent Protection Bit Lock (PPB Lock)
The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to "1", the PPBs cannot be changed. When cleared ("0"), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after powerup or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is "0". Each DYB is individually modifiable through the DYB Write Command. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state - meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected.
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Preliminary
By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the socalled Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are non-volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to "1". Setting the PPB Lock disables all program and erase commands to the non-volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed; for example, to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation. The WP#/ACC write protect pin adds a final level of hardware protection to sectors SA1-133, SA1-134, SA2-0 and SA2-1. When this pin is low it is not possible to change the contents of these sectors. These sectors generally hold system boot code. The WP#/ACC pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. For customers who are concerned about malicious viruses there is another level of security - the persistently locked state. To persistently protect a given sector or sector group, the PPBs associated with that sector need to be set to "1". Once all PPBs are programmed to the desired settings, the PPB Lock should be set to "1". Setting the PPB Lock automatically disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock "freezes" the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. The best protection is achieved by executing the PPB lock bit set command early in the boot code, and protect the boot code by holding WP#/ACC = VIL. Table 8 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector. In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock.
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 s before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sector. The programming of the DYB, PPB, and PPB lock for a given sector can be verified by writing a DYB/PPB/PPB lock verify command to the device. There is an alternative means of reading the protection status. Take RESET# to VIL and hold WE# at VIH.(The high voltage A9 Autoselect Mode also works for reading the status of the PPBs). Scanning the addresses (A18-A11) while (A6, A1, A0) = (0, 1, 0) will produce a logical `1" code at device output DQ0 for a protected sector or a "0" for an unprotected sector. In this mode, the other addresses are don't cares. Address location with A1 = VIL are reserved for autoselect manufacturer and device codes.
Persistent Sector Protection Mode Locking Bit
Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode.
Password Protection Mode
The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences between the Persistent Sector Protection and the Password Sector Protection Mode: When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 s delay for each "password check." This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password.
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
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Preliminary
Password and Password Mode Locking Bit
In order to select the Password sector protection scheme, the customer must first program the password. The password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: Permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. Disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed.
64-bit Password
The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see "Password Verify Command"). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device.
Write Protect (WP#)
The Write Protect feature provides a hardware method of protecting the upper two and lower two sectors without using VID. This function is provided by the WP# pin and overrides the previously discussed High Voltage Sector Protection method. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 4 Kword sectors on both ends of the flash array independent of whether it was previously protected or unprotected. If the system asserts VIH on the WP#/ACC pin, the device reverts the upper two and lower two sectors to whether they were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in the High Voltage Sector Protection. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
Persistent Protection Bit Lock
The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a "1" when the Password Mode Lock Bit is not set. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode.
High Voltage Sector Protection
Sector protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (VID) to be placed on the RESET# pin. Refer to Figure 1 for details on this procedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle.
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
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Preliminary
START PLSCNT = 1 RESET# = VID Wait 4 s Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address
START PLSCNT = 1 RESET# = VID Wait 4 s
Temporary Sector Unprotect Mode
No
First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A7-A0 = 00000010 Wait 100 s Verify Sector Protect: Write 40h to sector address with A7-A0 = 00000010 Read from sector address with A7-A0 = 00000010 No
First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address
No
Temporary Sector Unprotect Mode
Sector Unprotect: Write 60h to sector address with A7-A0 = 01000010 Reset PLSCNT = 1 Wait 1.2 ms Verify Sector Unprotect: Write 40h to sector address with A7-A0 = 00000010
Increment PLSCNT
No No PLSCNT = 25? Yes Remove VID from RESET# Data = 01h?
Increment PLSCNT
Yes
No Yes No
Read from sector address with A7-A0 = 00000010 Set up next sector address
Protect another sector? No Remove VID from RESET#
PLSCNT = 1000? Yes Remove VID from RESET#
Data = 00h? Yes
Write reset command
Sector Protect complete Write reset command Device failed
Last sector verified? Yes Remove VID from RESET#
No
Write reset command Sector Unprotect complete
Sector Protect complete
Sector Protect Algorithm
Write reset command Device failed Sector Unprotect complete
Sector Unprotect Algorithm
Figure 1. In-System Sector Protection/Sector Unprotection Algorithms
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. 2 shows the algorithm, and 21 shows the timing diagrams, for this feature. While PPB lock is set, the device cannot enter the Temporary Sector Unprotection Mode.
START
RESET# = VID (Note 1) Perform Erase or Program Operations
RESET# = VIH
Temporary Sector Unprotect Completed (Note 2)
Notes: 1. All protected sectors unprotected (If WP#/ACC = VIL, upper two and lower two sectors will remain protected). 2. All previously protected sectors are protected once again
Figure 2. Temporary Sector Unprotect Operation
SecSiTM (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN) The 128-word SecSi sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. The SecSi sector is located at addresses 000000h-00007Fh in both Persistent Protection mode and Password Protection mode. It uses indicator bits (DQ6, DQ7) to indicate the factory-locked and customer-locked status of the part. The system accesses the SecSi Sector through a command sequence (see the Enter SecSiTM Sector/Exit SecSi Sector Command Sequence). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled.
Factory-Locked Area (64 words)
The factory-locked area of the SecSi Sector (000000h-00003Fh) is locked when the part is shipped, whether or not the area was programmed at the factory. The
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
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Preliminary
SecSi Sector Factory-locked Indicator Bit (DQ7) is permanently set to a "1". Optional Spansion programming services can program the factory-locked area with a random ESN, a customer-defined code, or any combination of the two. Because only Spansion can program and protect the factory-locked area, this method ensures the security of the ESN once the product is shipped to the field. Contact your local sales office for details on using Spansion's programming services. Note that the ACC function and unlock bypass modes are not available when the SecSi sector is enabled.
Customer-Lockable Area (64 words)
The customer-lockable area of the SecSi Sector (000040h-00007Fh) is shipped unprotected, which allows the customer to program and optionally lock the area as appropriate for the application. The SecSi Sector Customer-locked Indicator Bit (DQ6) is shipped as "0" and can be permanently locked to "1" by issuing the SecSi Protection Bit Program Command. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The Customer-lockable SecSi Sector area can be protected using one of the following procedures: Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 1, except that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector Region without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way.
SecSi Sector Protection Bits
The SecSi Sector Protection Bits prevent programming of the SecSi Sector memory area. Once set, the SecSi Sector memory area contents are non-modifiable.
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
START RESET# = VIH or VID Wait 1 s Write 60h to any address If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected.
Remove VIH or VID from RESET#
Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0
Write reset command SecSi Sector Protect Verify complete
Figure 3. SecSi Sector Protect Verify
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Write Pulse "Glitch" Protection
Noise pulses of less than 3 ns (typical) on OE#, CE#, or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
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Preliminary
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 9-12. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 9-12. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100. Contact your local sales office for copies of these documents.
Table 9.
Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
CFI Query Identification String
Description
Query Unique ASCII string "QRY"
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
Table 10.
Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0027h 0036h 0000h 0000h 0003h 0000h 0009h 0000h 0004h 0000h 0004h 0000h
System Interface String
Description
VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 11. Device Geometry Definition
Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 0018h (PL127J) 0017h (PL064J) 0016h (PL032J) 0001h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 00FDh (PL127J) 007Dh (PL064J) 003Dh (PL032J) 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h Device Size = 2N byte Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Description
Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100)
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
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Preliminary
Table 12.
Addresses 40h 41h 42h 43h 44h 45h Data 0050h 0052h 0049h 0031h 0033h TBD
Primary Vendor-Specific Extended Query
Description
Query-unique ASCII string "PRI" Major version number, ASCII (reflects modifications to the silicon) Minor version number, ASCII (reflects modifications to the CFI table) Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 07 = Advanced Sector Protection Simultaneous Operation 00 = Not Supported, X = Number of Sectors excluding Bank 1 Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 00h = Uniform device, 01h = Both top and bottom boot with write protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom Program Suspend 0 = Not supported, 1 = Supported Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3
46h 47h 48h 49h
0002h 0001h 0001h 0007h (PLxxxJ) 00E7h (PL127J) 0077h (PL064J) 003Fh (PL032J) 0000h 0002h (PLxxxJ) 0085h 0095h
4Ah
4Bh 4Ch 4Dh 4Eh
4Fh
0001h
50h 57h
0001h 0004h 0027h (PL127J) 0017h (PL064J) 000Fh (PL032J) 0060h (PL127J) 0030h (PL064J) 0018h (PL032J) 0060h (PL127J) 0030h (PL064J) 0018h (PL032J)
58h
59h
5Ah
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
Table 12.
Addresses 5Bh Data 0027h (PL127J) 0017h (PL064J) 000Fh (PL032J)
Primary Vendor-Specific Extended Query (Continued)
Description Bank 4 Region Information X = Number of Sectors in Bank 4
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
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Preliminary
Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations. Table 13 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristic section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return a bank to the read (or erasesuspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The AC Characteristic table provides the read parameters, and Figure 12 shows the timing diagram.
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode.
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. Table 13 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 3 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erasesuspend-read mode if the bank was previously in Erase Suspend).
Enter SecSiTM Sector/Exit SecSi Sector Command Sequence
The SecSi Sector region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 13 shows the address and data requirements for both command sequences. See also "SecSiTM (Secured Silicon) Sector Flash Memory Region" for further information. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 13 shows the address and data requirements for the program command sequence. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
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Preliminary
operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Note that the SecSi Sector, autoselect and CFI functions are unavailable when the SecSi Sector is enabled. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from "0" back to a "1." Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1."
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program data to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 13 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (See Table 14) The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH any operation other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. 4 illustrates the algorithm for the program operation. Refer to the Erase/Program Operations table in the AC Characteristics section for parameters, and Figure 14 for timing diagrams.
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
Verify Data?
No
Yes No
Increment Address
Last Address?
Yes Programming Completed
Note: See Table 13 for program command sequence.
Figure 4. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 13 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation are ignored. Note that SecSi Sector, autoselect, and CFI functions are unavailable when a [program/ erase] operation is in progress. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity.
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
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Preliminary
5 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the AC Characteristics section for parameters, and Figure 16 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 13 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise erasure may begin. Any sector erase address and command following the exceeded timeout may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system must rewrite the command sequence and any additional addresses and commands. Note that SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. 5 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the AC Characteristics section for parameters, and Figure 16 section for timing diagrams.
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
START
Write Erase Command Sequence (Notes 1, 2)
Data Poll to Erasing Bank from System Embedded Erase algorithm in progress No Data = FFh?
Yes Erasure Completed
Notes: 1. See Table 13 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer.
Figure 5. Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 80 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 35 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. Addresses are "don't-cares" when writing the Erase suspend command. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program
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Preliminary
operation using the DQ7 or DQ6 status bits, just as in the standard Word Program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. Refer to the SecSiTM Sector Addresses and the Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command (address bits are don't care). The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Command should be reissued to improve program margin. If the SecSi Sector Protection Bit is verified as programmed without margin, the SecSi Sector Protection Bit Program Command should be reissued to improve program margin. After programming a PPB, two additional cycles are needed to determine whether the PPB has been programmed with margin. If the PPB has been programmed without margin, the program command should be reissued to improve the program margin. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased without margin, the erase command should be reissued to improve the program margin. The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sector Protection Status command to the device. Note that there is no single command to independently verify the programming of a DYB for a given sector group.
Command Definitions Tables
Table 13.
Command (Notes)
Read (Note 5) Reset (Note 6) Manufacturer ID Device ID (Note 10) SecSi Sector Factory Protect (Note 8) Sector Group Protect Verify (Note 9) Program Chip Erase Sector Erase Program/Erase Suspend (Note 11) Program/Erase Resume (Note 12) Cycles Addr RA XXX 555 555 555 555 555 555 555 BA BA
Memory Array Command Definitions
Bus Cycles (Notes 1-4) Data RD F0 AA AA AA AAA AA AA AA B0 30 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 (BA) 555 (BA) 555 (BA) 555 (BA) 555 555 555 555 90 90 90 90 A0 80 80 (BA) X00 (BA) X01 X03 (SA) X02 PA 555 555 01 227E (Note 8) XX00/ XX01 PD AA AA 2AA 2AA 55 55 555 SA 10 30 (BA) X0E (Note 10) (BA) X0F (Note 10) Addr Data Addr Data Addr Data Addr Data Addr Data
1 1 4 6 4 4 4 6 6 1 1
Autoselect (Note 7)
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
Table 13.
Command (Notes)
CFI Query (Note 13) Accelerated Program (Note 15) Unlock Bypass Entry (Note 15) Unlock Bypass Program (Note 15) Unlock Bypass Erase (Note 15) Unlock Bypass CFI (Notes 13, 15) Unlock Bypass Reset (Note 15) Cycles Addr 55 XX 555 XX XX XX XXX
Memory Array Command Definitions
Bus Cycles (Notes 1-4) Data 98 A0 AA A0 80 98 90 XXX 00 PA 2AA PA XX PD 55 PD 10 555 20 Addr Data Addr Data Addr Data Addr Data Addr Data
1 2 3 2 2 1 2
Legend: BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by PL127J: Amax:A20, PL064J: Amax:A19, PL032J: Amax:A18. PA = Program Address (Amax:A0). Addresses latch on falling edge of WE# or CE# pulse, whichever happens later. PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells in table denote read cycles. All other cycles are write operations. 4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don't cares. 5. No unlock or command cycles required when bank is reading array data. 6. The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend) when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information). 7. Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to obtain manufacturer ID or device ID information. See Autoselect Command Sequence section for more information. 8. The data is C4h for factory and customer locked, 84h for factory locked and 04h for not locked.
RA = Read Address (Amax:A0). RD = Read Data (DQ15:DQ0) from location RA. SA = Sector Address (Amax:A12) for verifying (in autoselect mode) or erasing. WD = Write Data. See "Configuration Register" definition for specific write data. Data latched on rising edge of WE#. X = Don't care
9. The data is 00h for an unprotected sector group and 01h for a protected sector group. 10. Device ID must be read across cycles 4, 5, and 6. PL127J (X0Eh = 2220h, X0Fh = 2200h),PL064J (X0Eh = 2202h, X0Fh = 2201h), PL032J (X0Eh = 220Ah, X0Fh = 2201h). 11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode. Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address. 12. Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address. 13. Command is valid when device is ready to read array data or when device is in autoselect mode. 14. WP#/ACC must be at VID during the entire operation of command. 15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to the reading array.
Table 14.
Command (Notes) Reset SecSi Sector Entry SecSi Sector Exit SecSi Protection Bit Program (Notes 5, 6) SecSi Protection Bit Status Password Program (Notes 5, 7, 8) Password Verify (Notes 6, 8, 9) Cycles Addr XXX 555 555 555 555 555 555 555 555 Data F0 AA AA AA AA AA AA AA AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 55 Addr
Sector Protection Command Definitions
Bus Cycles (Notes 1-4) Addr Data Addr Data Addr Data Addr Data
Data Addr Data 555 555 555 555 555 555 555 555 88 90 60 60 38 C8 28 60
1 3 4 6 5 4 4
XX OW OW XX[0-3]
00 68 48 PD[0-3] OW OW 48 RD(0) OW RD(0)
PWA[0-3] PWD[0-3] PWA[0] (SA)WP PWD[0] 68 PWA[1] PWD[1] PWA[2] PWD[2] PWA[3] (SA)WP 48 (SA)WP RD(0) PWD[3]
Password Unlock (Notes 7 7, 10, 11) PPB Program (Notes 5, 6, 12) 6
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S29PL127J/S29PL064J/S29PL032J for MCP
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Preliminary
Table 14.
PPB Status All PPB Erase (Notes 5, 6, 13, 14) PPB Lock Bit Set PPB Lock Bit Status (Note 15) DYB Write (Note 7) DYB Erase (Note 7) DYB Status (Note 6) PPMLB Program (Notes 5, 6, 12) PPMLB Status (Note 5) SPMLB Program (Notes 5, 6, 12) SPMLB Status (Note 5) 4 6 3 4 4 4 4 6 5 6 5 555 555 555 555 555 555 555 555 555 555 555 AA AA AA AA AA AA AA AA AA AA AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 55 55 55 55
Sector Protection Command Definitions
555 555 555 555 555 555 555 555 555 555 555 90 60 78 58 48 48 58 60 60 60 60 SA SA SA SA PL PL SL SL RD(1) X1 X0 RD(0) 68 48 68 48 PL PL SL SL 48 RD(0) 48 RD(0) SL RD(0) PL RD(0) (SA)WP WP RD(0) 60 (SA) 40 (SA)WP RD(0)
Legend: DYB = Dynamic Protection Bit OW = Address (A7:A0) is (00011010) PD[3:0] = Password Data (1 of 4 portions) PPB = Persistent Protection Bit PWA = Password Address. A1:A0 selects portion of password. PWD = Password Data being verified. PL = Password Protection Mode Lock Address (A7:A0) is (00001010) Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells in table denote read cycles. All other cycles are write operations. 4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don't cares. 5. The reset command returns device to reading array. 6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, program command must be issued and verified again. 7. Data is latched on the rising edge of WE#. 8. Entire command sequence must be entered for each portion of password.
RD(0) = Read Data DQ0 for protection indicator bit. RD(1) = Read Data DQ1 for PPB Lock status. SA = Sector Address where security command applies. Address bits Amax:A12 uniquely select any sector. SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010) WP = PPB Address (A7:A0) is (00000010) X = Don't care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit 9. Command sequence returns FFh if PPMLB is set. 10. The password is written over four consecutive cycles, at addresses 0-3. 11. A 2 s timeout is required between any two portions of password. 12. A 100 s timeout is required between cycles 4 and 5. 13. A 1.2 ms timeout is required between cycles 4 and 5. 14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB overerasure. 15. DQ1 = 1 if PPB locked, 0 if unlocked.
Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 15 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence.
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 400 s, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15-DQ0 on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ15-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ15-DQ0 may be still invalid. Valid data on DQ15-DQ0 will appear on successive read cycles. Table 15 shows the outputs for Data# Polling on DQ7. 6 shows the Data# Polling algorithm. 18 in the AC Characteristic section shows the Data# Polling timing diagram.
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
53
Preliminary
START
Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No No
DQ5 = 1?
Yes Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
Figure 6. Data# Polling Algorithm
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. Table 15 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 400 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 15 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit algorithm. Figure 19 in "Read Operation Timings" shows the toggle bit timing diagrams. Figure 20 shows the differences between DQ2 and DQ6 in graphical form. See also the DQ2: Toggle Bit II.
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
55
Preliminary
START
Read Byte (DQ7-DQ0) Address =VA Read Byte (DQ7-DQ0) Address =VA
Toggle Bit = Toggle? Yes
No
No
DQ5 = 1?
Yes Read Byte Twice (DQ7-DQ0) Address = VA
Toggle Bit = Toggle?
No
Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete
Note: The system should recheck the toggle bit even if DQ5 = "1" because the toggle bit may stop toggling as DQ5 changes to "1." See the DQ6: Toggle Bit I and DQ2: Toggle Bit II for more information.
Figure 7. Toggle Bit Algorithm
DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 15 to compare outputs for DQ2 and DQ6. Figure 7 shows the toggle bit algorithm in flowchart form, and the DQ2: Toggle Bit II explains the algorithm. See also the DQ6: Toggle Bit I. Figure 19 shows the toggle bit timing diagram. Figure 20 shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and
56
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 7).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed. The device may output a "1" on DQ5 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a "1." Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a "0" to a "1." See also the Sector Erase Command Sequence. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 15 shows the status of DQ3 relative to the other status bits.
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
57
Preliminary
Table 15.
Status Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Erase-SuspendRead Erase Suspended Sector Non-Erase Suspended Sector
Write Operation Status
DQ7 (Note 2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0
Erase Suspend Mode
Erase-Suspend-Program
Notes: 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
58
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
Absolute Maximum Ratings
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . .-65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . .-65C to +125C Voltage with Respect to Ground VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V RESET# (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +13.0 V WP#/ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +10.5 V All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is -0.5 V. During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on pin A9, OE#, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
20 ns +0.8 V -0.5 V -2.0 V 20 ns
20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns
20 ns
20 ns
Maximum Negative Overshoot Waveform
Maximum Positive Overshoot Waveform
Figure 8. Maximum Overshoot Waveforms
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
59
Preliminary
Operating Ranges
Operating ranges define those limits between which the functionality of the device is guaranteed.
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
Wireless Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C
Supply Voltages
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7-3.1 V VIO (see Note) . . 1.65-1.95 V (for PL127J) or 2.7-3.1 V (for all PLxxxJ devices)
Notes: For all AC and DC specifications, VIO = VCC; contact your local sales office for other VIO options.
60
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
DC Characteristics
Table 16.
Parameter Symbol ILI ILIT ILR ILO ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 ICC9 VIL VIH VHH VID Parameter Description Input Load Current A9, OE#, RESET# Input Load Current Reset Leakage Current Output Leakage Current VCC Active Read Current (Notes 1, 2) VCC Active Write Current (Notes 2, 3) VCC Standby Current (Note 2) VCC Reset Current (Note 2) Automatic Sleep Mode (Notes 2, 4) VCC Active Read-While-Program Current (Notes 1, 2) VCC Active Read-While-Erase Current (Notes 1, 2) VCC Active Program-While-EraseSuspended Current (Notes 2, 5) VCC Active Page Read Current (Note 2) Input Low Voltage
CMOS Compatible
Test Conditions Min Typ Max 1.0 35 35 1.0 5 MHz 10 MHz 15 45 15 0.2 0.2 0.2 5 MHz 10 MHz 5 MHz 10 MHz 21 46 21 46 17 10 -0.4 -0.5 VIO-0.4 2.0 8.5 11.5 25 55 25 5 5 5 45 70 45 70 25 15 0.4 0.8 VIO+0.4 VCC+0.3 9.5 12.5 0.1 0.4 VIO-0.1 2.4 2.3 2.5 Unit A A A A mA mA A A A mA
VIN = VSS to VCC, VCC = VCC max VCC = VCC max; VID= 12.5 V VCC = VCC max; VID= 12.5 V VOUT = VSS to VCC, OE# = VIH VCC = VCC max OE# = VIH, VCC = VCC max (Note 1) OE# = VIH, WE# = VIL CE#, RESET#, WP#/ACC = VIO 0.3 V RESET# = VSS 0.3 V VIH = VIO 0.3 V; VIL = VSS 0.3 V OE# = VIH, OE# = VIH, OE# = VIH OE# = VIH, 8 word Page Read VIO = 1.65-1.95 V (PL127J) VIO = 2.7-3.6 V VIO = 1.65-1.95 V (PL127J) VIO = 2.7-3.6 V VCC = 3.0 V 10% VCC = 3.0 V 10% IOL = 100 A, VCC = VCC min, VIO = 1.65- 1.95 V (PL127J) IOL = 2.0 mA, VCC = VCC min, VIO = 2.7-3.6 V IOH = -100 A, VCC = VCC min, VIO = 1.65- 1.95 V (PL127J) IOH = -2.0 mA, VCC = VCC min, VIO = 2.7-3.6 V
mA mA mA V V V V V V V V V V V
Input High Voltage Voltage for ACC Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect
VOL
Output Low Voltage
VOH
Output High Voltage
VLKO
Low VCC Lock-Out Voltage (Note 5)
Notes: 1. The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 1 mA. 5. Not 100% tested. 6. Valid CE1#/CE2# conditions: (CE1# = VIL, CE2# = VIH,) or (CE1# = VIH, CE2# = VIL) or (CE1# = VIH, CE2# = VIH)
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
61
Preliminary
AC Characteristic
Test Conditions
3.6 V
Device Under Test CL 6.2 k
2.7 k
Device Under Test CL
VIO = 3.0 V Note: Diodes are IN3064 or equivalent
VIO = 1.8 V (PL127J)
Figure 9.
Test Setups
Table 17. Test Specifications
Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times VIO = 1.8 V (PL127J) VIO = 3.0 V Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels VIO = 1.8 V (PL127J) VIO = 3.0 V 0.0 - 1.8 0.0-3.0 VIO/2 VIO/2 V V V All Speeds 1 TTL gate 30 5 pF ns Unit
62
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
SWITCHING WAVEFORMS
Table 18. KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
VIO 0.0 V
In
VIO/2
Measurement Level
VIO/2
Output
Figure 10. Input Waveforms and Measurement Levels
VCC RampRate
All DC characteristics are specified for a VCC ramp rate > 1V/100 s and VCC >=VCCQ - 100 mV. If the VCC ramp rate is < 1V/100 s, a hardware reset required.+
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
63
Preliminary
Read Operations
Table 19.
Parameter JEDEC tAVAV tAVQV tELQV Std. tRC tACC tCE Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay CE#, OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Max Min Min Min 55 55 55 55 20 20
Read-Only Operations
Speed Options 60 60 60 60 25 25 16 16 5 0 10 65 65 65 65 30 30 70 70 70 70 Unit ns ns ns ns ns ns ns ns ns ns
tPACC Page Access Time tGLQV tEHQZ tGHQZ tAXQX tOE tDF tDF tOH Output Enable to Output Delay Chip Enable to Output High Z (Note 3) Output Enable to Output High Z (Notes 1, 3) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 3) Output Enable Hold Time (Note 1) Read Toggle and Data# Polling
tOEH
Notes: 1. Not 100% tested. 2. See Figure 9 and Table 17 for test specifications 3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC /2. The time from OE# high to the data bus driven to VCC /2 is taken as tDF. 4. For 70pF Output Load Capacitance, 2 ns will be added to the above tACC,tCE,tPACC,tOE values for all speed grades
tRC Addresses CE# tRH tRH OE# tOEH WE# HIGH Z Data RESET# RY/BY# Valid Data tCE tOH HIGH Z tOE tDF Addresses Stable tACC
0V
Figure 11. Read Operation Timings
64
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
Amax-A3
Same Page
A2-A0
Aa
tACC
Ab
tPACC
Ac
tPACC tPACC
Ad
Data CE# OE#
Qa
Qb
Qc
Qd
Figure 12. Page Read Operation Timings
Reset
Table 20. Hardware Reset (RESET#)
Parameter JEDEC Std tReady tReady tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Max Max Min Min Min Min All Speed Options 35 500 500 50 20 0 Unit s ns ns ns s ns
Note: Not 100% tested.
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
65
Preliminary
RY/BY#
CE#, OE# tRH RESET# tRP tReady
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# tRB CE#, OE#
RESET# tRP
Figure 13. Reset Timings
66
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
Erase/Program Operations
Table 21. Erase and Program Operations
Parameter JEDEC tAVAV tAVWL Std tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tCS tCH tWP tWPH tSR/W tWHWH1 tWHWH1 tWHWH2 tWHWH1 tWHWH1 tWHWH2 tVCS tRB tBUSY Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Programming Operation (Note 2) Accelerated Programming Operation (Note 2) Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Write Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Max 35 20 0 6 4 0.5 50 0 90 25 0 10 0 0 0 40 25 30 0 30 55 55 Speed Options 60 60 0 15 35 65 65 70 70 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s sec s ns ns
Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information.
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
67
Preliminary
Timing Diagrams
Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# Status DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles)
tCH
A0h
VCC tVCS
Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address
Figure 14.
Program Operation Timings
VHH
WP#/ACC
VIL or VIH tVHH tVHH
VIL or VIH
Figure 15.
Accelerated Program Timing Diagram
68
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
Preliminary
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA
555h for chip erase
Read Status Data
VA tAH
VA
CE#
OE# tWP WE# tCS tDS
tCH
tWPH
tWHWH2
tDH Data 55h 30h
10 for Chip Erase Status DOUT
tBUSY RY/BY# tVCS VCC
tRB
Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status"
Figure 16. Chip/Sector Erase Operation Timings
tWC Addresses tAS CE#
Valid PA
tRC
Valid RA
tWC
Valid PA
tWC
Valid PA
tAH tACC tCE tOE OE# tOEH tWP WE# tWPH tDS tDH Data
Valid In
tAS tCPH
tAH
tCP
tGHWL
tDF tOH
Valid Out Valid In Valid In
tSR/W
WE# Controlled Write Cycle Read Cycle CE# Controlled Write Cycles
Figure 17. Back-to-back Read/Write Cycle Timings
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Preliminary
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7
High Z
VA
VA
tOE tDF
Complement
Complement
True
Valid Data
High Z
DQ6-DQ0 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle
Figure 18. Data# Polling Timings (During Embedded Algorithms)
tAHT Addresses
tAS
tAHT tASO CE# tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data
Valid Status
tCEPH
tOE
Valid Status Valid Status
Valid Data
(first read) RY/BY#
(second read)
(stops toggling)
Notes: 1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle
Figure 19. Toggle Bit Timings (During Embedded Algorithms)
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Preliminary
Enter Embedded Erasing WE#
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program Erase Suspend Read
Erase Resume Erase Erase Complete
Erase Suspend Read
DQ6
DQ2 Note:Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE#
or CE# to toggle DQ2 and DQ6.
Figure 20.
DQ2 vs. DQ6
Protect/Unprotect
Table 22. Temporary Sector Unprotect
Parameter JEDEC Std tVIDR tVHH tRSP tRRB Description VID Rise and Fall Time (See Note) VHH Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min Min Min Min All Speed Options 500 250 4 4 Unit ns ns s s
Note: Not 100% tested.
VID RESET# VIL or VIH tVIDR Program or Erase Command Sequence CE# tVIDR VIL or VIH VID
WE# tRSP RY/BY# tRRB
Figure 21. Temporary Sector Unprotect Timing Diagram
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VID VIH
RESET#
SA, A6, A1, A0
Valid* Sector Group Protect/Unprotect
Valid* Verify 40h
Valid*
Data 1 s CE#
60h
60h
Status
Sector Group Protect: 150 s Sector Group Unprotect: 15 ms
WE#
OE#
Notes: 1. For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 22.
Sector/Sector Block Protect and Unprotect Timing Diagram
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Preliminary
Controlled Erase Operations
Table 23. Alternate CE# Controlled Erase and Program Operations
Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH1 tWHWH2 Std tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Programming Operation (Note 2) Accelerated Programming Operation (Note 2) Sector Erase Operation (Note 2) Min Min Min Min Min Min Min Min Min Min Typ Typ Typ 35 20 6 4 0.5 30 25 0 0 0 0 40 25 55 55 Speed Options 60 60 0 35 30 65 65 70 70 Unit ns ns ns ns ns ns ns ns ns ns s s sec
Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information.
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Preliminary
555 for program 2AA for erase
PA for program SA for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device
Table 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings
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Table 25.
Parameter Sector Erase Time
PL127J
Erase And Programming Performance
Typ (Note 1)
0.5 135 71 39 6 4 50.4 25.2 12.6
Max (Note 2)
2 216 113.6 62.4 100 60 200 50.4 25.2
Unit
sec sec sec sec s s sec sec sec
Comments Excludes 00h programming prior to erasure (Note 4) Excludes system level overhead (Note 5)
Chip Erase Time
PL064J PL032J
Word Program Time Accelerated Word Program Time Chip Program Time (Note 3)
PL127J PL064J PL032J
Notes: 1. Typical program and erase times assume the following conditions: 25xC, 3.0 V VCC, 100,000 cycles. Additionally, programming typicals assume checkerboard pattern. All values are subject to change. 2. Under worst case conditions of 90xC, VCC = 2.7 V, 100,000 cycles. All values are subject to change. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 13 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
BGA Pin Capacitance
Parameter Symbol CIN COUT CIN2 CIN3 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance WP#/ACC Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Typ 6.3 7.0 5.5 11 Max 7 8 8 12 Unit pF pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
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S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
S29GLxxxN MirrorBitTM Flash Family
S29GL512N, S29GL256N, S29GL128N 512 Megabit, 256 Megabit, and 128 Megabit, 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit process technology
Data Sheet
ADVANCE INFORMATION
Distinctive Characteristics
Architectural Advantages
Single power supply operation -- 3 volt read, erase, and program operations Enhanced VersatileI/OTM control -- All input levels (address, control, and DQ input levels) and outputs are determined by voltage on VIO input. VIO range is 1.65 to VCC Manufactured on 110 nm MirrorBit process technology Secured Silicon Sector region -- 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence -- May be programmed and locked at the factory or by the customer Flexible sector architecture -- S29GL512N: Five hundred twelve 64 Kword (128 Kbyte) sectors -- S29GL256N: Two hundred fifty-six 64 Kword (128 Kbyte) sectors -- S29GL128N: One hundred twenty-eight 64 Kword (128 Kbyte) sectors Compatibility with JEDEC standards -- Provides pinout and software compatibility for singlepower supply flash, and superior inadvertent write protection 100,000 erase cycles per sector typical 20-year data retention typical
Software & Hardware Features
Software features -- Program Suspend & Resume: read other sectors before programming operation is completed -- Erase Suspend & Resume: read/program other sectors before an erase operation is completed -- Data# polling & toggle bits provide status -- Unlock Bypass Program command reduces overall multiple-word programming time -- CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices Hardware features -- Advanced Sector Protection -- WP#/ACC input accelerates programming time (when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings -- Hardware reset input (RESET#) resets device -- Ready/Busy# output (RY/BY#) detects program or erase cycle completion
Performance Characteristics
High performance -- 90 ns access time (S29GL128N, S29GL256N, S29GL512N) -- 8-word/16-byte page read buffer -- 25 ns page read times -- 16-word/32-byte write buffer reduces overall programming time for multiple-word updates Low power consumption (typical values at 3.0 V, 5 MHz) -- 25 mA typical active read current; -- 50 mA typical erase/program current -- 1 A typical standby mode current
Publication Number S29GLxxxN_MCP
Revision A
Amendment 1
Issue Date December 15, 2004
This document contains information on a product under development at Spansion LLC. The information is intended to help you evaluate this product. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
Advance
Information
General Description
The S29GL512/256/128N family of devices are 3.0V single power flash memory manufactured using 110 nm MirrorBit technology. The S29GL512N is a 512 Mbit, organized as 33,554,432 words or 67,108,864 bytes. The S29GL256N is a 256 Mbit, organized as 16,777,216 words or 33,554,432 bytes. The S29GL128N is a 128 Mbit, organized as 8,388,608 words or 16,777,216 bytes. The device can be programmed either in the host system or in standard EPROM programmers. Access times as fast as 90 ns (S29GL128N, S29GL256N, S29GL512N) are available. Note that each access time has a specific operating voltage range (VCC) and an I/O voltage range (VIO), as specified in the "Product Selector Guide" section. The devices are offered in a 56-pin TSOP or 64-ball Fortified BGA package. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a VCC input, a high-voltage accelerated program (WP#/ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The devices are entirely command set compatible with the JEDEC singlepower-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. The Enhanced VersatileI/OTM (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on all input levels (address, chip control, and DQ input levels) to the same voltage level that is asserted on the VIO pin. This allows the device to operate in a 1.8 V or 3 V system environment as required. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. Persistent Sector Protection provides in-system, command-enabled protection of any combination of sectors using a single power supply at VCC. Password Sector Protection prevents unauthorized write and erase operations in any combination of sectors through a user-defined 64-bit password. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be
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tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. The Write Protect (WP#/ACC) feature protects the first or last sector by asserting a logic low on the WP# pin. MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.
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Product Selector Guide
S29GL512N
Part Number VCC = 2.7-3.6 V VCC = 3.0-3.6V Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page access time (ns) Max. OE# Access Time (ns) VIO = 2.7-3.6 V VIO = 1.65-1.95 V VIO = 3.0-3.6V 90 90 90 25 25 100 100 25 25 110 110 25 25 110 110 30 30 S29GL512N 10 11 11
Speed Option
S29GL256N
Part Number VCC = 2.7-3.6 V VCC = Regulated (3.0-3.6V) Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page access time (ns) Max. OE# Access Time (ns) VIO = 2.7-3.6 V VIO = 1.65-1.95 V VIO = Regulated (3.0-3.6V) 90 90 90 25 25 100 100 25 25 110 110 25 25 110 110 30 30 S29GL256N 10 11 11
Speed Option
S29GL128N
Part Number VCC = 2.7-3.6 V VCC = Regulated (3.0-3.6V) Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page access time (ns) Max. OE# Access Time (ns) VIO = 2.7-3.6 V VIO = 1.65-1.95 V VIO = Regulated (3.0-3.6V) 90 90 90 25 25 100 100 25 25 110 110 25 25 110 110 30 30 S29GL128N 10 11 11
Speed Option
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Block Diagram
VCC VSS VIO RESET# WE# WP#/ACC
RY/BY#
Sector Switches Erase Voltage Generator
DQ15-DQ0 (A-1)
Input/Output Buffers
State Control Command Register
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
AMax**-A0
Notes: 1. AMax GL512N = A24, AMax GL256N = A23, AMax GL128N = A22
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Pin Description
A24-A0 A23-A0 A22-A0 DQ14-DQ0 DQ15/A-1 CE# OE# WE# WP#/ACC RESET# RY/BY# VCC VIO VSS NC = = = = = = = = = = = = 25 Address inputs (512 Mb) 24 Address inputs (256 Mb) 23 Address inputs (128 Mb) 15 Data inputs/outputs DQ15 (Data input/output, word mode), A-1 (LSB Address input Chip Enable input Output Enable input Write Enable input Hardware Write Protect input; Acceleration input Hardware Reset Pin input Ready/Busy output 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) Output Buffer power Device Ground Pin Not Connected Internally
= = =
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Logic Symbol
S29GL512N
25 A24-A0 CE# OE# WE# WP#/ACC RESET# VIO RY/BY# DQ15-DQ0 (A-1) 16 or 8
S29GL256N
24 A23-A0 CE# OE# WE# WP#/ACC RESET# VIO RY/BY# DQ15-DQ0 (A-1) 16 or 8
S29GL128N
23 A22-A0 CE# OE# WE# WP#/ACC RESET# VIO RY/BY# DQ15-DQ0 (A-1) 16 or 8
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Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Table 1.
Operation Read Write (Program/Erase) Accelerated Program Standby Output Disable Reset VCC CE# L L L OE# L H H X H X
Device Bus Operations
WE# H L L X H X RESET# H H H VCC 0.3 V H L WP#/ ACC X Note 2 VHH H X X Addresses (Note 1) AIN AIN AIN X X X DQ0-DQ15 DOUT (Note 3) (Note 3) High-Z High-Z High-Z
0.3 V
L X
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 11.5-12.5V, X = Don't Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are AMax:A0 in word mode. Sector addresses are AMax:A16 in both modes.
2. If WP# = VIL, the first or last sector group remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as determined by the method described in "Write Protect (WP#)". All sectors are unprotected when shipped from the factory (The Secured Silicon Sector may be factory protected depending on version ordered.)
3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2, Figure 4, and Figure 5).
VersatileIOTM (VIO) Control
The VersatileIOTM (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on CE# and DQ I/Os to the same voltage level that is asserted on VIO. See Ordering Information for VIO options on this device. For example, a VI/O of 1.65 V to 3.6 V allows for I/O at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8-V or 3-V devices on the same data bus.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory
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content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" on page 127 for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 11 for the timing diagram. Refer to the DC Characteristics table for the active current specification on reading array data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 8 words/16 bytes. The appropriate page is selected by the higher address bits A(max)-A3. Address bits A2-A0 determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is de-asserted and reasserted for a subsequent access, the access time is tACC or tCE. Fast page mode accesses are obtained by keeping the "read-page addresses" constant and changing the "intra-read page" addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The "Word Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2, Table 4, and Table 5 indicate the address space that each sector occupies. Refer to the DC Characteristics table for the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. See "Write Buffer" for more information.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory.
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If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at VIH.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to the "Autoselect Mode" section on page 113 and "Autoselect Command Sequence" section on page 127 sections for more information.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VIO 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. Refer to the "DC Characteristics" section on page 151 for the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to the "DC Characteristics" section on page 151 for the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
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Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (ICC5). If RESET# is held at VIL but not within VSS0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Refer to the AC Characteristics tables for RESET# parameters and to Figure 13 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
Table 2. Sector Address Table-S29GL512N
Sector Size (Kbytes/ Kwords) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0000000-000FFFF 0010000-001FFFF 0020000-002FFFF 0030000-003FFFF 0040000-004FFFF 0050000-005FFFF 0060000-006FFFF 0070000-007FFFF 0080000-008FFFF 0090000-009FFFF 00A0000-00AFFFF 00B0000-00BFFFF 00C0000-00CFFFF 00D0000-00DFFFF 00E0000-00EFFFF 00F0000-00FFFFF 0100000-010FFFF 0110000-011FFFF 0120000-012FFFF 0130000-013FFFF 0140000-014FFFF 0150000-015FFFF 0160000-016FFFF 0170000-017FFFF
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A24-A16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
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Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0180000-018FFFF 0190000-019FFFF 01A0000-01AFFFF 01B0000-01BFFFF 01C0000-01CFFFF 01D0000-01DFFFF 01E0000-01EFFFF 01F0000-01FFFFF 0200000-020FFFF 0210000-021FFFF 0220000-022FFFF 0230000-023FFFF 0240000-024FFFF 0250000-025FFFF 0260000-026FFFF 0270000-027FFFF 0280000-028FFFF 0290000-029FFFF 02A0000-02AFFFF 02B0000-02BFFFF 02C0000-02CFFFF 02D0000-02DFFFF 02E0000-02EFFFF 02F0000-02FFFFF 0300000-030FFFF 0310000-031FFFF 0320000-032FFFF 0330000-033FFFF 0340000-034FFFF 0350000-035FFFF 0360000-036FFFF 0370000-037FFFF 0380000-038FFFF 0390000-039FFFF 03A0000-03AFFFF
Sector SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A24-A16 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
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Information
Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 03B0000-03BFFFF 03C0000-03CFFFF 03D0000-03DFFFF 03E0000-03EFFFF 03F0000-03FFFFF 0400000-040FFFF 0410000-041FFFF 0420000-042FFFF 0430000-043FFFF 0440000-044FFFF 0450000-045FFFF 0460000-046FFFF 0470000-047FFFF 0480000-048FFFF 0490000-049FFFF 04A0000-04AFFFF 04B0000-04BFFFF 04C0000-04CFFFF 04D0000-04DFFFF 04E0000-04EFFFF 04F0000-04FFFFF 0500000-050FFFF 0510000-051FFFF 0520000-052FFFF 0530000-053FFFF 0540000-054FFFF 0550000-055FFFF 0560000-056FFFF 0570000-057FFFF 0580000-058FFFF 0590000-059FFFF 05A0000-05AFFFF 05B0000-05BFFFF 05C0000-05CFFFF 05D0000-05DFFFF
Sector SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A24-A16 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Information
Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 05E0000-05EFFFF 05F0000-05FFFFF 0600000-060FFFF 0610000-061FFFF 0620000-062FFFF 0630000-063FFFF 0640000-064FFFF 0650000-065FFFF 0660000-066FFFF 0670000-067FFFF 0680000-068FFFF 0690000-069FFFF 06A0000-06AFFFF 06B0000-06BFFFF 06C0000-06CFFFF 06D0000-06DFFFF 06E0000-06EFFFF 06F0000-06FFFFF 0700000-070FFFF 0710000-071FFFF 0720000-072FFFF 0730000-073FFFF 0740000-074FFFF 0750000-075FFFF 0760000-076FFFF 0770000-077FFFF 0780000-078FFFF 0790000-079FFFF 07A0000-07AFFFF 07B0000-07BFFFF 07C0000-07CFFFF 07D0000-07DFFFF 07E0000-07EFFFF 07F0000-07FFFFF 0800000-080FFFF
Sector SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
A24-A16 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
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Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0810000-081FFFF 0820000-082FFFF 0830000-083FFFF 0840000-084FFFF 0850000-085FFFF 0860000-086FFFF 0870000-087FFFF 0880000-088FFFF 0890000-089FFFF 08A0000-08AFFFF 08B0000-08BFFFF 08C0000-08CFFFF 08D0000-08DFFFF 08E0000-08EFFFF 08F0000-08FFFFF 0900000-090FFFF 0910000-091FFFF 0920000-092FFFF 0930000-093FFFF 0940000-094FFFF 0950000-095FFFF 0960000-096FFFF 0970000-097FFFF 0980000-098FFFF 0990000-099FFFF 09A0000-09AFFFF 09B0000-09BFFFF 09C0000-09CFFFF 09D0000-09DFFFF 09E0000-09EFFFF 09F0000-09FFFFF 0A00000-0A0FFFF 0A10000-0A1FFFF 0A20000-0A2FFFF 0A30000-0A3FFFF
Sector SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 SA160 SA161 SA162 SA163 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
A24-A16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
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Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0A40000-0A4FFFF 0A50000-0A5FFFF 0A60000-0A6FFFF 0A70000-0A7FFFF 0A80000-0A8FFFF 0A90000-0A9FFFF 0AA0000-0AAFFFF 0AB0000-0ABFFFF 0AC0000-0ACFFFF 0AD0000-0ADFFFF 0AE0000-0AEFFFF 0AF0000-0AFFFFF 0B00000-0B0FFFF 0B10000-0B1FFFF 0B20000-0B2FFFF 0B30000-0B3FFFF 0B40000-0B4FFFF 0B50000-0B5FFFF 0B60000-0B6FFFF 0B70000-0B7FFFF 0B80000-0B8FFFF 0B90000-0B9FFFF 0BA0000-0BAFFFF 0BB0000-0BBFFFF 0BC0000-0BCFFFF 0BD0000-0BDFFFF 0BE0000-0BEFFFF 0BF0000-0BFFFFF 0C00000-0C0FFFF 0C10000-0C1FFFF 0C20000-0C2FFFF 0C30000-0C3FFFF 0C40000-0C4FFFF 0C50000-0C5FFFF 0C60000-0C6FFFF
Sector SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
A24-A16 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
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Information
Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0C70000-0C7FFFF 0C80000-0C8FFFF 0C90000-0C9FFFF 0CA0000-0CAFFFF 0CB0000-0CBFFFF 0CC0000-0CCFFFF 0CD0000-0CDFFFF 0CE0000-0CEFFFF 0CF0000-0CFFFFF 0D00000-0D0FFFF 0D10000-0D1FFFF 0D20000-0D2FFFF 0D30000-0D3FFFF 0D40000-0D4FFFF 0D50000-0D5FFFF 0D60000-0D6FFFF 0D70000-0D7FFFF 0D80000-0D8FFFF 0D90000-0D9FFFF 0DA0000-0DAFFFF 0DB0000-0DBFFFF 0DC0000-0DCFFFF 0DD0000-0DDFFFF 0DE0000-0DEFFFF 0DF0000-0DFFFFF 0E00000-0E0FFFF 0E10000-0E1FFFF 0E20000-0E2FFFF 0E30000-0E3FFFF 0E40000-0E4FFFF 0E50000-0E5FFFF 0E60000-0E6FFFF 0E70000-0E7FFFF 0E80000-0E8FFFF 0E90000-0E9FFFF
Sector SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230 SA231 SA232 SA233 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
A24-A16 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
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Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0EA0000-0EAFFFF 0EB0000-0EBFFFF 0EC0000-0ECFFFF 0ED0000-0EDFFFF 0EE0000-0EEFFFF 0EF0000-0EFFFFF 0F00000-0F0FFFF 0F10000-0F1FFFF 0F20000-0F2FFFF 0F30000-0F3FFFF 0F40000-0F4FFFF 0F50000-0F5FFFF 0F60000-0F6FFFF 0F70000-0F7FFFF 0F80000-0F8FFFF 0F90000-0F9FFFF 0FA0000-0FAFFFF 0FB0000-0FBFFFF 0FC0000-0FCFFFF 0FD0000-0FDFFFF 0FE0000-0FEFFFF 0FF0000-0FFFFFF 1000000-100FFFF 1010000-101FFFF 1020000-102FFFF 1030000-103FFFF 1040000-104FFFF 1050000-105FFFF 1060000-106FFFF 1070000-107FFFF 1080000-108FFFF 1090000-109FFFF 10A0000-10AFFFF 10B0000-10BFFFF 10C0000-10CFFFF
Sector SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
A24-A16 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
94
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Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 10D0000-10DFFFF 10E0000-10EFFFF 10F0000-10FFFFF 1100000-110FFFF 1110000-111FFFF 1120000-112FFFF 1130000-113FFFF 1140000-114FFFF 1150000-115FFFF 1160000-116FFFF 1170000-117FFFF 1180000-118FFFF 1190000-119FFFF 11A0000-11AFFFF 11B0000-11BFFFF 11C0000-11CFFFF 11D0000-11DFFFF 11E0000-11EFFFF 11F0000-11FFFFF 1200000-120FFFF 1210000-121FFFF 1220000-122FFFF 1230000-123FFFF 1240000-124FFFF 1250000-125FFFF 1260000-126FFFF 1270000-127FFFF 1280000-128FFFF 1290000-129FFFF 12A0000-12AFFFF 12B0000-12BFFFF 12C0000-12CFFFF 12D0000-12DFFFF 12E0000-12EFFFF 12F0000-12FFFFF
Sector SA269 SA270 SA271 SA272 SA273 SA274 SA275 SA276 SA277 SA278 SA279 SA280 SA281 SA282 SA283 SA284 SA285 SA286 SA287 SA288 SA289 SA290 SA291 SA292 SA293 SA294 SA295 SA296 SA297 SA298 SA299 SA300 SA301 SA302 SA303 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A24-A16 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 1300000-130FFFF 1310000-131FFFF 1320000-132FFFF 1330000-133FFFF 1340000-134FFFF 1350000-135FFFF 1360000-136FFFF 1370000-137FFFF 1380000-138FFFF 1390000-139FFFF 13A0000-13AFFFF 13B0000-13BFFFF 13C0000-13CFFFF 13D0000-13DFFFF 13E0000-13EFFFF 13F0000-13FFFFF 1400000-140FFFF 1410000-141FFFF 1420000-142FFFF 1430000-143FFFF 1440000-144FFFF 1450000-145FFFF 1460000-146FFFF 1470000-147FFFF 1480000-148FFFF 1490000-149FFFF 14A0000-14AFFFF 14B0000-14BFFFF 14C0000-14CFFFF 14D0000-14DFFFF 14E0000-14EFFFF 14F0000-14FFFFF 1500000-150FFFF 1510000-151FFFF 1520000-152FFFF
Sector SA304 SA305 SA306 SA307 SA308 SA309 SA310 SA311 SA312 SA313 SA314 SA315 SA316 SA317 SA318 SA319 SA320 SA321 SA322 SA323 SA324 SA325 SA326 SA327 SA328 SA329 SA330 SA331 SA332 SA333 SA334 SA335 SA336 SA337 SA338 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A24-A16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
96
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Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 1530000-153FFFF 1540000-154FFFF 1550000-155FFFF 1560000-156FFFF 1570000-157FFFF 1580000-158FFFF 1590000-159FFFF 15A0000-15AFFFF 15B0000-15BFFFF 15C0000-15CFFFF 15D0000-15DFFFF 15E0000-15EFFFF 15F0000-15FFFFF 1600000-160FFFF 1610000-161FFFF 1620000-162FFFF 1630000-163FFFF 1640000-164FFFF 1650000-165FFFF 1660000-166FFFF 1670000-167FFFF 1680000-168FFFF 1690000-169FFFF 16A0000-16AFFFF 16B0000-16BFFFF 16C0000-16CFFFF 16D0000-16DFFFF 16E0000-16EFFFF 16F0000-16FFFFF 1700000-170FFFF 1710000-171FFFF 1720000-172FFFF 1730000-173FFFF 1740000-174FFFF 1750000-175FFFF
Sector SA339 SA340 SA341 SA342 SA343 SA344 SA345 SA346 SA347 SA348 SA349 SA350 SA351 SA352 SA353 SA354 SA355 SA356 SA357 SA358 SA359 SA360 SA361 SA362 SA363 SA364 SA365 SA366 SA367 SA368 SA369 SA370 SA371 SA372 SA373 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A24-A16 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
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Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 1760000-176FFFF 1770000-177FFFF 1780000-178FFFF 1790000-179FFFF 17A0000-17AFFFF 17B0000-17BFFFF 17C0000-17CFFFF 17D0000-17DFFFF 17E0000-17EFFFF 17F0000-17FFFFF 1800000-180FFFF 1810000-181FFFF 1820000-182FFFF 1830000-183FFFF 1840000-184FFFF 1850000-185FFFF 1860000-186FFFF 1870000-187FFFF 1880000-188FFFF 1890000-189FFFF 18A0000-18AFFFF 18B0000-18BFFFF 18C0000-18CFFFF 18D0000-18DFFFF 18E0000-18EFFFF 18F0000-18FFFFF 1900000-190FFFF 1910000-191FFFF 1920000-192FFFF 1930000-193FFFF 1940000-194FFFF 1950000-195FFFF 1960000-196FFFF 1970000-197FFFF 1980000-198FFFF
Sector SA374 SA375 SA376 SA377 SA378 SA379 SA380 SA381 SA382 SA383 SA384 SA385 SA386 SA387 SA388 SA389 SA390 SA391 SA392 SA393 SA394 SA395 SA396 SA397 SA398 SA399 SA400 SA401 SA402 SA403 SA404 SA405 SA406 SA407 SA408 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A24-A16 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
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Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 1990000-199FFFF 19A0000-19AFFFF 19B0000-19BFFFF 19C0000-19CFFFF 19D0000-19DFFFF 19E0000-19EFFFF 19F0000-19FFFFF 1A00000-1A0FFFF 1A10000-1A1FFFF 1A20000-1A2FFFF 1A30000-1A3FFFF 1A40000-1A4FFFF 1A50000-1A5FFFF 1A60000-1A6FFFF 1A70000-1A7FFFF 1A80000-1A8FFFF 1A90000-1A9FFFF 1AA0000-1AAFFFF 1AB0000-1ABFFFF 1AC0000-1ACFFFF 1AD0000-1ADFFFF 1AE0000-1AEFFFF 1AF0000-1AFFFFF 1B00000-1B0FFFF 1B10000-1B1FFFF 1B20000-1B2FFFF 1B30000-1B3FFFF 1B40000-1B4FFFF 1B50000-1B5FFFF 1B60000-1B6FFFF 1B70000-1B7FFFF 1B80000-1B8FFFF 1B90000-1B9FFFF 1BA0000-1BAFFFF 1BB0000-1BBFFFF
Sector SA409 SA410 SA411 SA412 SA413 SA414 SA415 SA416 SA417 SA418 SA419 SA420 SA421 SA422 SA423 SA424 SA425 SA426 SA427 SA428 SA429 SA430 SA431 SA432 SA433 SA434 SA435 SA436 SA437 SA438 SA439 SA440 SA441 SA442 SA443 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A24-A16 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
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Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 1BC0000-1BCFFFF 1BD0000-1BDFFFF 1BE0000-1BEFFFF 1BF0000-1BFFFFF 1C00000-1C0FFFF 1C10000-1C1FFFF 1C20000-1C2FFFF 1C30000-1C3FFFF 1C40000-1C4FFFF 1C50000-1C5FFFF 1C60000-1C6FFFF 1C70000-1C7FFFF 1C80000-1C8FFFF 1C90000-1C9FFFF 1CA0000-1CAFFFF 1CB0000-1CBFFFF 1CC0000-1CCFFFF 1CD0000-1CDFFFF 1CE0000-1CEFFFF 1CF0000-1CFFFFF 1D00000-1D0FFFF 1D10000-1D1FFFF 1D20000-1D2FFFF 1D30000-1D3FFFF 1D40000-1D4FFFF 1D50000-1D5FFFF 1D60000-1D6FFFF 1D70000-1D7FFFF 1D80000-1D8FFFF 1D90000-1D9FFFF 1DA0000-1DAFFFF 1DB0000-1DBFFFF 1DC0000-1DCFFFF 1DD0000-1DDFFFF 1DE0000-1DEFFFF
Sector SA444 SA445 SA446 SA447 SA448 SA449 SA450 SA451 SA452 SA453 SA454 SA455 SA456 SA457 SA458 SA459 SA460 SA461 SA462 SA463 SA464 SA465 SA466 SA467 SA468 SA469 SA470 SA471 SA472 SA473 SA474 SA475 SA476 SA477 SA478 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A24-A16 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Table 2.
Sector Address Table-S29GL512N (Continued)
Sector Size (Kbytes/ Kwords) 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 1DF0000-1DFFFFF 1E00000-1E0FFFF 1E10000-1E1FFFF 1E20000-1E2FFFF 1E30000-1E3FFFF 1E40000-1E4FFFF 1E50000-1E5FFFF 1E60000-1E6FFFF 1E70000-1E7FFFF 1E80000-1E8FFFF 1E90000-1E9FFFF 1EA0000-1EAFFFF 1EB0000-1EBFFFF 1EC0000-1ECFFFF 1ED0000-1EDFFFF 1EE0000-1EEFFFF 1EF0000-1EFFFFF 1F00000-1F0FFFF 1F10000-1F1FFFF 1F20000-1F2FFFF 1F30000-1F3FFFF 1F40000-1F4FFFF 1F50000-1F5FFFF 1F60000-1F6FFFF 1F70000-1F7FFFF 1F80000-1F8FFFF 1F90000-1F9FFFF 1FA0000-1FAFFFF 1FB0000-1FBFFFF 1FC0000-1FCFFFF 1FD0000-1FDFFFF 1FE0000-1FEFFFF 1FF0000-1FFFFFF
Sector SA479 SA480 SA481 SA482 SA483 SA484 SA485 SA486 SA487 SA488 SA489 SA490 SA491 SA492 SA493 SA494 SA495 SA496 SA497 SA498 SA499 SA500 SA501 SA502 SA503 SA504 SA505 SA506 SA507 SA508 SA509 SA510 SA511 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A24-A16 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Table 3. Sector Address Table-S29GL256N
Sector Size (Kbytes/ Kwords) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0000000-000FFFF 0010000-001FFFF 0020000-002FFFF 0030000-003FFFF 0040000-004FFFF 0050000-005FFFF 0060000-006FFFF 0070000-007FFFF 0080000-008FFFF 0090000-009FFFF 00A0000-00AFFFF 00B0000-00BFFFF 00C0000-00CFFFF 00D0000-00DFFFF 00E0000-00EFFFF 00F0000-00FFFFF 0100000-010FFFF 0110000-011FFFF 0120000-012FFFF 0130000-013FFFF 0140000-014FFFF 0150000-015FFFF 0160000-016FFFF 0170000-017FFFF 0180000-018FFFF 0190000-019FFFF 01A0000-01AFFFF 01B0000-01BFFFF 01C0000-01CFFFF 01D0000-01DFFFF 01E0000-01EFFFF 01F0000-01FFFFF 0200000-020FFFF 0210000-021FFFF
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
A23-A16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0
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Table 3. Sector Address Table-S29GL256N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0220000-022FFFF 0230000-023FFFF 0240000-024FFFF 0250000-025FFFF 0260000-026FFFF 0270000-027FFFF 0280000-028FFFF 0290000-029FFFF 02A0000-02AFFFF 02B0000-02BFFFF 02C0000-02CFFFF 02D0000-02DFFFF 02E0000-02EFFFF 02F0000-02FFFFF 0300000-030FFFF 0310000-031FFFF 0320000-032FFFF 0330000-033FFFF 0340000-034FFFF 0350000-035FFFF 0360000-036FFFF 0370000-037FFFF 0380000-038FFFF 0390000-039FFFF 03A0000-03AFFFF 03B0000-03BFFFF 03C0000-03CFFFF 03D0000-03DFFFF 03E0000-03EFFFF 03F0000-03FFFFF 0400000-040FFFF 0410000-041FFFF 0420000-042FFFF 0430000-043FFFF 0440000-044FFFF
Sector SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0
A23-A16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0
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Table 3. Sector Address Table-S29GL256N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0450000-045FFFF 0460000-046FFFF 0470000-047FFFF 0480000-048FFFF 0490000-049FFFF 04A0000-04AFFFF 04B0000-04BFFFF 04C0000-04CFFFF 04D0000-04DFFFF 04E0000-04EFFFF 04F0000-04FFFFF 0500000-050FFFF 0510000-051FFFF 0520000-052FFFF 0530000-053FFFF 0540000-054FFFF 0550000-055FFFF 0560000-056FFFF 0570000-057FFFF 0580000-058FFFF 0590000-059FFFF 05A0000-05AFFFF 05B0000-05BFFFF 05C0000-05CFFFF 05D0000-05DFFFF 05E0000-05EFFFF 05F0000-05FFFFF 0600000-060FFFF 0610000-061FFFF 0620000-062FFFF 0630000-063FFFF 0640000-064FFFF 0650000-065FFFF 0660000-066FFFF 0670000-067FFFF
Sector SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A23-A16 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
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Table 3. Sector Address Table-S29GL256N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0680000-068FFFF 0690000-069FFFF 06A0000-06AFFFF 06B0000-06BFFFF 06C0000-06CFFFF 06D0000-06DFFFF 06E0000-06EFFFF 06F0000-06FFFFF 0700000-070FFFF 0710000-071FFFF 0720000-072FFFF 0730000-073FFFF 0740000-074FFFF 0750000-075FFFF 0760000-076FFFF 0770000-077FFFF 0780000-078FFFF 0790000-079FFFF 07A0000-07AFFFF 07B0000-07BFFFF 07C0000-07CFFFF 07D0000-07DFFFF 07E0000-07EFFFF 07F0000-07FFFFF 0800000-080FFFF 0810000-081FFFF 0820000-082FFFF 0830000-083FFFF 0840000-084FFFF 0850000-085FFFF 0860000-086FFFF 0870000-087FFFF 0880000-088FFFF 0890000-089FFFF 08A0000-08AFFFF
Sector SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
A23-A16 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1
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Table 3. Sector Address Table-S29GL256N (Continued)
Sector Size (Kbytes/ Kwords) 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 08B0000-08BFFFF 08C0000-08CFFFF 08D0000-08DFFFF 08E0000-08EFFFF 08F0000-08FFFFF 0900000-090FFFF 0910000-091FFFF 0920000-092FFFF 0930000-093FFFF 0940000-094FFFF 0950000-095FFFF 0960000-096FFFF 0970000-097FFFF 0980000-098FFFF 0990000-099FFFF 09A0000-09AFFFF 09B0000-09BFFFF 09C0000-09CFFFF 09D0000-09DFFFF 09E0000-09EFFFF 09F0000-09FFFFF 0A00000-0A0FFFF 0A10000-0A1FFFF 0A20000-0A2FFFF 0A30000-0A3FFFF 0A40000-0A4FFFF 0A50000-0A5FFFF 0A60000-0A6FFFF 0A70000-0A7FFFF 0A80000-0A8FFFF 0A90000-0A9FFFF 0AA0000-0AAFFFF 0AB0000-0ABFFFF 0AC0000-0ACFFFF 0AD0000-0ADFFFF
Sector SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A23-A16 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1
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Table 3. Sector Address Table-S29GL256N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0AE0000-0AEFFFF 0AF0000-0AFFFFF 0B00000-0B0FFFF 0B10000-0B1FFFF 0B20000-0B2FFFF 0B30000-0B3FFFF 0B40000-0B4FFFF 0B50000-0B5FFFF 0B60000-0B6FFFF 0B70000-0B7FFFF 0B80000-0B8FFFF 0B90000-0B9FFFF 0BA0000-0BAFFFF 0BB0000-0BBFFFF 0BC0000-0BCFFFF 0BD0000-0BDFFFF 0BE0000-0BEFFFF 0BF0000-0BFFFFF 0C00000-0C0FFFF 0C10000-0C1FFFF 0C20000-0C2FFFF 0C30000-0C3FFFF 0C40000-0C4FFFF 0C50000-0C5FFFF 0C60000-0C6FFFF 0C70000-0C7FFFF 0C80000-0C8FFFF 0C90000-0C9FFFF 0CA0000-0CAFFFF 0CB0000-0CBFFFF 0CC0000-0CCFFFF 0CD0000-0CDFFFF 0CE0000-0CEFFFF 0CF0000-0CFFFFF 0D00000-0D0FFFF
Sector SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A23-A16 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
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Table 3. Sector Address Table-S29GL256N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0D10000-0D1FFFF 0D20000-0D2FFFF 0D30000-0D3FFFF 0D40000-0D4FFFF 0D50000-0D5FFFF 0D60000-0D6FFFF 0D70000-0D7FFFF 0D80000-0D8FFFF 0D90000-0D9FFFF 0DA0000-0DAFFFF 0DB0000-0DBFFFF 0DC0000-0DCFFFF 0DD0000-0DDFFFF 0DE0000-0DEFFFF 0DF0000-0DFFFFF 0E00000-0E0FFFF 0E10000-0E1FFFF 0E20000-0E2FFFF 0E30000-0E3FFFF 0E40000-0E4FFFF 0E50000-0E5FFFF 0E60000-0E6FFFF 0E70000-0E7FFFF 0E80000-0E8FFFF 0E90000-0E9FFFF 0EA0000-0EAFFFF 0EB0000-0EBFFFF 0EC0000-0ECFFFF 0ED0000-0EDFFFF 0EE0000-0EEFFFF 0EF0000-0EFFFFF 0F00000-0F0FFFF 0F10000-0F1FFFF 0F20000-0F2FFFF 0F30000-0F3FFFF
Sector SA209 SA210 SA211 SA212 SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230 SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A23-A16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
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Table 3. Sector Address Table-S29GL256N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0F40000-0F4FFFF 0F50000-0F5FFFF 0F60000-0F6FFFF 0F70000-0F7FFFF 0F80000-0F8FFFF 0F90000-0F9FFFF 0FA0000-0FAFFFF 0FB0000-0FBFFFF 0FC0000-0FCFFFF 0FD0000-0FDFFFF 0FE0000-0FEFFFF 0FF0000-0FFFFFF
Sector SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A23-A16 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1
Table 4. Sector Address Table-S29GL128N
Sector Size (Kbytes/ Kwords) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0000000-000FFFF 0010000-001FFFF 0020000-002FFFF 0030000-003FFFF 0040000-004FFFF 0050000-005FFFF 0060000-006FFFF 0070000-007FFFF 0080000-008FFFF 0090000-009FFFF 00A0000-00AFFFF 00B0000-00BFFFF 00C0000-00CFFFF 00D0000-00DFFFF 00E0000-00EFFFF 00F0000-00FFFFF 0100000-010FFFF 0110000-011FFFF
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
A22-A16 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
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Table 4.
Sector Address Table-S29GL128N (Continued)
Sector Size (Kbytes/ Kwords) 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0120000-012FFFF 0130000-013FFFF 0140000-014FFFF 0150000-015FFFF 0160000-016FFFF 0170000-017FFFF 0180000-018FFFF 0190000-019FFFF 01A0000-01AFFFF 01B0000-01BFFFF 01C0000-01CFFFF 01D0000-01DFFFF 01E0000-01EFFFF 01F0000-01FFFFF 0200000-020FFFF 0210000-021FFFF 0220000-022FFFF 0230000-023FFFF 0240000-024FFFF 0250000-025FFFF 0260000-026FFFF 0270000-027FFFF 0280000-028FFFF 0290000-029FFFF 02A0000-02AFFFF 02B0000-02BFFFF 02C0000-02CFFFF 02D0000-02DFFFF 02E0000-02EFFFF 02F0000-02FFFFF 0300000-030FFFF 0310000-031FFFF 0320000-032FFFF 0330000-033FFFF 0340000-034FFFF
Sector SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
A22-A16 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1
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Table 4.
Sector Address Table-S29GL128N (Continued)
Sector Size (Kbytes/ Kwords) 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0350000-035FFFF 0360000-036FFFF 0370000-037FFFF 0380000-038FFFF 0390000-039FFFF 03A0000-03AFFFF 03B0000-03BFFFF 03C0000-03CFFFF 03D0000-03DFFFF 03E0000-03EFFFF 03F0000-03FFFFF 0400000-040FFFF 0410000-041FFFF 0420000-042FFFF 0430000-043FFFF 0440000-044FFFF 0450000-045FFFF 0460000-046FFFF 0470000-047FFFF 0480000-048FFFF 0490000-049FFFF 04A0000-04AFFFF 04B0000-04BFFFF 04C0000-04CFFFF 04D0000-04DFFFF 04E0000-04EFFFF 04F0000-04FFFFF 0500000-050FFFF 0510000-051FFFF 0520000-052FFFF 0530000-053FFFF 0540000-054FFFF 0550000-055FFFF 0560000-056FFFF 0570000-057FFFF
Sector SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A22-A16 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
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Table 4.
Sector Address Table-S29GL128N (Continued)
Sector Size (Kbytes/ Kwords) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 0580000-058FFFF 0590000-059FFFF 05A0000-05AFFFF 05B0000-05BFFFF 05C0000-05CFFFF 05D0000-05DFFFF 05E0000-05EFFFF 05F0000-05FFFFF 0600000-060FFFF 0610000-061FFFF 0620000-062FFFF 0630000-063FFFF 0640000-064FFFF 0650000-065FFFF 0660000-066FFFF 0670000-067FFFF 0680000-068FFFF 0690000-069FFFF 06A0000-06AFFFF 06B0000-06BFFFF 06C0000-06CFFFF 06D0000-06DFFFF 06E0000-06EFFFF 06F0000-06FFFFF 0700000-070FFFF 0710000-071FFFF 0720000-072FFFF 0730000-073FFFF 0740000-074FFFF 0750000-075FFFF 0760000-076FFFF 0770000-077FFFF 0780000-078FFFF 0790000-079FFFF 07A0000-07AFFFF
Sector SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
A22-A16 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0
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Table 4.
Sector Address Table-S29GL128N (Continued)
Sector Size (Kbytes/ Kwords) 1 0 0 1 1 1 0 1 0 1 128/64 128/64 128/64 128/64 128/64 Address Range (in hexadecimal) 07B0000-07BFFFF 07C0000-07CFFFF 07D0000-07DFFFF 07E0000-07EFFFF 07F0000-07FFFFF
Sector SA123 SA124 SA125 SA126 SA127 1 1 1 1 1 1 1 1 1 1
A22-A16 1 1 1 1 1 0 1 1 1 1
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector group protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A3, A2, A1, and A0 must be as shown in Table 5. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 2). Table 5 shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 12. This method does not require VID. Refer to the Autoselect Command Sequence section for more information.
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Table 5. Autoselect Codes, (High Voltage Method)
Description Manufacturer ID: Spansion Product Device ID Device ID Device ID S29GL128N S29GL256N S29GL512N Cycle 1 Cycle 2 Cycle 3 Cycle 1 Cycle 2 Cycle 3 Cycle 1 Cycle 2 Cycle 3 L L H SA X VID X L X L L H X X VID X L X L L H X X VID X L X L L H X X VID X L X CE# OE# WE # H A22 A14 to to A15 A10 X X A9 A8 to A7 X A6 A5 to A4 X A3 to A2 L L H H L H H L H H L A1 A0 DQ8 to DQ15 00 22 22 22 22 22 22 22 22 22 X DQ7 to DQ0
L
L
VID
L
L L H H L H H L H H H
L H L H H L H H L H L
01h 7Eh 23h 01h 7Eh 22h 01h 7Eh 21h 01h 01h (protected), 00h (unprotected) 98h (factory locked), 18h (not factory locked)
Sector Group Protection Verification Secured Silicon Sector Indicator Bit (DQ7), WP# protects highest address sector Secured Silicon Sector Indicator Bit (DQ7), WP# protects lowest address sector
L
L
H
X
X
VID
X
L
X
L
H
H
X
L
L
H
X
X
VID
X
L
X
L
H
H
X
88h (factory locked), 08h (not factory locked)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care.
Sector Protection
The device features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups:
Persistent Sector Protection
A command sector protection method that replaces the old 12 V controlled protection method.
Password Sector Protection
A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted
WP# Hardware Protection
A write protect pin that can prevent program or erase operations in the outermost sectors. The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen.
Selecting a Sector Protection Mode
All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. If the customer decides to continue
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using the Persistent Sector Protection method, they must set the Persistent Sector Protection Mode Locking Bit. This will permanently set the part to operate only using Persistent Sector Protection. If the customer decides to use the password method, they must set the Password Mode Locking Bit. This will permanently set the part to operate only using password sector protection. It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the Password Mode Locking Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit has been set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. This is so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The device is shipped with all sectors unprotected. The factory offers the option of programming and protecting sectors at the factory prior to shipping the device through the ExpressFlashTM Service. Contact your sales representative for details. It is possible to determine whether a sector is protected or unprotected. See "Autoselect Command Sequence" section on page 127 for details.
Advanced Sector Protection
Advanced Sector Protection features several levels of sector protection, which can disable both the program and erase operations in certain sectors. Persistent Sector Protection is a method that replaces the old 12V controlled protection method. Password Sector Protection is a highly sophisticated protection method that requires a password before changes to certain sectors are permitted.
Lock Register
The Lock Register consists of 3 bits (DQ2, DQ1, and DQ0). These DQ2, DQ1, DQ0 bits of the Lock Register are programmable by the user. Users are not allowed to program both DQ2 and DQ1 bits of the Lock Register to the 00 state. If the user tries to program DQ2 and DQ1 bits of the Lock Register to the 00 state, the device will abort the Lock Register back to the default 11 state. The programming time of the Lock Register is same as the typical word programming time without utilizing the Write Buffer of the device. During a Lock Register programming sequence execution, the DQ6 Toggle Bit I will toggle until the programming of the Lock Register has completed to indicate programming status. All Lock Register bits are readable to allow users to verify Lock Register statuses. The Customer Secured Silicon Sector Protection Bit is DQ0, Persistent Protection Mode Lock Bit is DQ1, and Password Protection Mode Lock Bit is DQ2 are accessible by all users. Each of these bits are non-volatile. DQ15-DQ3 are reserved and must be 1's when the user tries to program the DQ2, DQ1, and DQ0 bits of the Lock Register. The user is not required to program DQ2, DQ1 and DQ0 bits of the Lock Register at the same time. This allows users to lock the Secured Silicon Sector and then set the device either permanently into Password Protection Mode or Persistent Protection Mode and then lock the Secured Silicon Sector at separate instances and time frames. Secured Silicon Sector Protection allows the user to lock the Secured Silicon Sector area
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Persistent Protection Mode Lock Bit allows the user to set the device permanently to operate in the Persistent Protection Mode Password Protection Mode Lock Bit allows the user to set the device permanently to operate in the Password Protection Mode
Table 6. Lock Register
DQ15-3 Don't Care DQ2 Password Protection Mode Lock Bit DQ1 Persistent Protection Mode Lock Bit DQ0 Secured Silicon Sector Protection Bit
Persistent Sector Protection
The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing flexibility by providing three different sector protection states: Dynamically Locked-The sector is protected and can be changed by a simple command Persistently Locked-A sector is protected and cannot be changed Unlocked-The sector is unprotected and can be changed by a simple command In order to achieve these states, three types of "bits" are going to be used:
Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYB bits are in the "unprotected state". Each DYB is individually modifiable through the DYB Set Command and DYB Clear Command. When the parts are first shipped, all of the Persistent Protect Bits (PPB) are cleared into the unprotected state. The DYB bits and PPB Lock bit are defaulted to power up in the cleared state or unprotected state - meaning the all PPB bits are changeable. The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPB bits cleared, the DYB bits control whether or not the sector is protected or unprotected. By issuing the DYB Set and DYB Clear command sequences, the DYB bits will be protected or unprotected, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and un-protected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYB bits maybe set or cleared as often as needed. The PPB bits allow for a more static, and difficult to change, level of protection. The PPB bits retain their state across power cycles because they are Non-Volatile. Individual PPB bits are set with a program command but must all be cleared as a group through an erase command. The PPB Lock Bit adds an additional level of protection. Once all PPB bits are programmed to the desired settings, the PPB Lock Bit may be set to the "freeze state". Setting the PPB Lock Bit to the "freeze state" disables all program and erase commands to the Non-Volatile PPB bits. In effect, the PPB Lock Bit locks the PPB bits into their current state. The only way to clear the PPB Lock Bit to the
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"unfreeze state" is to go through a power cycle, or hardware reset. The Software Reset command will not clear the PPB Lock Bit to the "unfreeze state". System boot code can determine if any changes to the PPB bits are needed e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock Bit to disable any further changes to the PPB bits during system operation. The WP# write protect pin adds a final level of hardware protection. When this pin is low it is not possible to change the contents of the WP# protected sectors. These sectors generally hold system boot code. So, the WP# pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Set command sequence is all that is necessary. The DYB Set and DYB Clear commands for the dynamic sectors switch the DYB bits to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be disabled to the "unfreeze state" by either putting the device through a power-cycle, or hardware reset. The PPB bits can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again to the "freeze state" will lock the PPB bits, and the device operates normally again. Note: to achieve the best protection, it's recommended to execute the PPB Lock Bit Set command early in the boot code, and protect the boot code by holding WP# = VIL.
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to each sector. If a PPB is programmed to the protected state through the "PPB Program" command, that sector will be protected from program or erase operations will be read-only. If a PPB requires erasure, all of the sector PPB bits must first be erased in parallel through the "All PPB Erase" command. The "All PPB Erase" command will preprogrammed all PPB bits prior to PPB erasing. All PPB bits erase in parallel, unlike programming where individual PPB bits are programmable. The PPB bits have the same endurance as the flash memory. Programming the PPB bit requires the typical word programming time without utilizing the Write Buffer. During a PPB bit programming and A11 PPB bit erasing sequence execution, the DQ6 Toggle Bit I will toggle until the programming of the PPB bit or erasing of all PPB bits has completed to indicate programming and erasing status. Erasing all of the PPB bits at once requires typical sector erase time. During the erasing of all PPB bits, the DQ3 Sector Erase Timer bit will output a 1 to indicate the erasure of all PPB bits are in progress. When the erasure of all PPB bits has completed, the DQ3 Sector Erase Timer bit will output a 0 to indicate that all PPB bits have been erased. Reading the PPB Status bit requires the initial access time of the device.
Persistent Protection Bit Lock (PPB Lock Bit)
A global volatile bit. When set to the "freeze state", the PPB bits cannot be changed. When cleared to the "unfreeze state", the PPB bits are changeable. There is only one PPB Lock Bit per device. The PPB Lock Bit is cleared to the "un-
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freeze state" after power-up or hardware reset. There is no command sequence to unlock or "unfreeze" the PPB Lock Bit. Configuring the PPB Lock Bit to the freeze state requires approximately 100ns. Reading the PPB Lock Status bit requires the initial access time of the device.
Table 7. Sector Protection Schemes
Protection States DYB Bit Unprotect Unprotect Unprotect Unprotect Protect Protect Protect Protect PPB Bit Unprotect Unprotect Protect Protect Unprotect Unprotect Protect Protect PPB Lock Bit Unfreeze Freeze Unfreeze Freeze Unfreeze Freeze Unfreeze Freeze Sector State Unprotected - PPB and DYB are changeable Unprotected - PPB not changeable, DYB is changeable Protected - PPB and DYB are changeable Protected - PPB not changeable, DYB is changeable Protected - PPB and DYB are changeable Protected - PPB not changeable, DYB is changeable Protected - PPB and DYB are changeable Protected - PPB not changeable, DYB is changeable
Table 7 contains all possible combinations of the DYB bit, PPB bit, and PPB Lock Bit relating to the status of the sector. In summary, if the PPB bit is set, and the PPB Lock Bit is set, the sector is protected and the protection cannot be removed until the next power cycle or hardware reset clears the PPB Lock Bit to "unfreeze state". If the PPB bit is cleared, the sector can be dynamically locked or unlocked. The DYB bit then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 s before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sector. The programming of the DYB bit, PPB bit, and PPB Lock Bit for a given sector can be verified by writing a DYB Status Read, PPB Status Read, and PPB Lock Status Read commands to the device. The Autoselect Sector Protection Verification outputs the OR function of the DYB bit and PPB bit per sector basis. When the OR function of the DYB bit and PPB bit is a 1, the sector is either protected by DYB or PPB or both. When the OR function of the DYB bit and PPB bit is a 0, the sector is unprotected through both the DYB and PPB.
Persistent Protection Mode Lock Bit
Like the Password Protection Mode Lock Bit, a Persistent Protection Mode Lock Bit exists to guarantee that the device remain in software sector protection. Once programmed, the Persistent Protection Mode Lock Bit prevents programming of the Password Protection Mode Lock Bit. This guarantees that a hacker could not place the device in Password Protection Mode. The Password Protection Mode Lock Bit resides in the "Lock Register".
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Password Sector Protection
The Password Sector Protection method allows an even higher level of security than the Persistent Sector Protection method. There are two main differences between the Persistent Sector Protection and the Password Sector Protection methods: When the device is first powered on, or comes out of a reset cycle, the PPB Lock Bit is set to the locked state, or the freeze state, rather than cleared to the unlocked state, or the unfreeze state. The only means to clear and unfreeze the PPB Lock Bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. The password is stored in a one-time programmable (OTP) region outside of the flash memory. Once the Password Protection Mode Lock Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear and unfreeze the PPB Lock Bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock Bit is cleared to the "unfreezed state", and the PPB bits can be altered. If they do not match, the flash device does nothing. There is a built-in 2 s delay for each "password check" after the valid 64-bit password has been entered for the PPB Lock Bit to be cleared to the "unfreezed state". This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password.
Password and Password Protection Mode Lock Bit
In order to select the Password Sector Protection method, the customer must first program the password. The factory recommends that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Read operations. Once the desired password is programmed in, the customer must then set the Password Protection Mode Lock Bit. This operation achieves two objectives: 1. It permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. 2. It also disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Sector Protection method is desired when programming the Password Protection Mode Lock Bit. More importantly, the user must be sure that the password is correct when the Password Protection Mode Lock Bit is programmed. Due to the fact that read operations are disabled, there is no means to read what the password is afterwards. If the password is lost after programming the Password Protection Mode Lock Bit, there will be no way to clear and unfreeze the PPB Lock Bit. The Password Protection Mode Lock Bit, once programmed, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Protection Mode Lock Bit is not erasable. Once Password Protection Mode Lock Bit is
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programmed, the Persistent Protection Mode Lock Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed.
64-bit Password
The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Password Read commands. The password function works in conjunction with the Password Protection Mode Lock Bit, which when programmed, prevents the Password Read command from reading the contents of the password on the pins of the device.
Persistent Protection Bit Lock (PPB Lock Bit)
A global volatile bit. The PPB Lock Bit is a volatile bit that reflects the state of the Password Protection Mode Lock Bit after power-up reset. If the Password Protection Mode Lock Bit is also programmed after programming the Password, the Password Unlock command must be issued to clear and unfreeze the PPB Lock Bit after a hardware reset (RESET# asserted) or a power-up reset. Successful execution of the Password Unlock command clears and unfreezes the PPB Lock Bit, allowing for sector PPB bits to be modified. Without issuing the Password Unlock command, while asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a the "freeze state". If the Password Protection Mode Lock Bit is not programmed, the device defaults to Persistent Protection Mode. In the Persistent Protection Mode, the PPB Lock Bit is cleared to the "unfreeze state" after power-up or hardware reset. The PPB Lock Bit is set to the "freeze state" by issuing the PPB Lock Bit Set command. Once set to the "freeze state" the only means for clearing the PPB Lock Bit to the "unfreeze state" is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode. Reading the PPB Lock Bit requires a 200ns access time.
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 bytes in length, and uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. The factory offers the device with the Secured Silicon Sector either customer lockable (standard shipping option) or factory locked (contact an AMD sales representative for ordering information). The customer-lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to program the sector after receiving the device. The customer-lockable version also has the Secured Silicon Sector Indicator Bit permanently set to a "0." The factory-locked version is always protected when shipped from the factory, and has the Secured Silicon Sector Indicator Bit permanently set to a "1." Thus, the Secured Silicon Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled.
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The Secured Silicon sector address space in this device is allocated as follows:
Secured Silicon Sector Address Range 000000h-000007h Determined by customer 000008h-00007Fh Unavailable Customer Lockable ESN Factory Locked ESN ExpressFlash Factory Locked ESN or determined by customer Determined by customer
The system accesses the Secured Silicon Sector through a command sequence (see "Write Protect (WP#)"). After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by the first sector (SA0). This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to sector SA0.
Customer Lockable: Secured Silicon Sector NOT Programmed or Protected At the Factory
Unless otherwise specified, the device is shipped such that the customer may program and protect the 256-byte Secured Silicon sector. The system may program the Secured Silicon Sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming command sequence. See "Command Definitions" . Programming and protecting the Secured Silicon Sector must be used with caution since, once protected, there is no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way. The Secured Silicon Sector area can be protected using one of the following procedures: Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect algorithm, except that RESET# may be at either VIH or VID. This allows in-system protection of the Secured Silicon Sector without raising any device pin to a high voltage. Note that this method is only applicable to the Secured Silicon Sector. To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm. Once the Secured Silicon Sector is programmed, locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing within the remainder of the array.
Factory Locked: Secured Silicon Sector Programmed and Protected At the Factory
In devices with an ESN, the Secured Silicon Sector is protected when the device is shipped from the factory. The Secured Silicon Sector cannot be modified in any way. An ESN Factory Locked device has an 16-byte random ESN at addresses 000000h-000007h. Please contact your sales representative for details on ordering ESN Factory Locked devices. Customers may opt to have their code programmed by the factory through the ExpressFlash service (Express Flash Factory Locked). The devices are then shipped from the factory with the Secured Silicon Sector permanently locked. Contact your sales representative for details on using the ExpressFlash service.
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Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or last sector group without using VID. Write Protect is one of two functions provided by the WP#/ACC input. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the first or last sector group independently of whether those sector groups were protected or unprotected using the method described in"Advanced Sector Protection" section on page 115. Note that if WP#/ACC is at VIL when the device is in the standby mode, the maximum input load current is increased. See the table in "DC Characteristics" section on page 151. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the first or last sector was previously set to be protected or unprotected using the method described in "Sector Group Protection and Unprotection". Note that WP# has an internal pullup; when unconnected, WP# is at VIH.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 12 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can
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then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 8-11. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 8-11. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact your sales representative for copies of these documents.
Table 8.
Addresses (x16) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
CFI Query Identification String
Description
Query Unique ASCII string "QRY"
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
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Table 9.
Addresses (x16) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0027h 0036h 0000h 0000h 0007h 0007h 000Ah 0000h 0001h 0005h 0004h 0000h
System Interface String
Description
VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
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Table 10.
Addresses (x16) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 001Ah 0019h 0018h 0002h 0000h 0005h 0000h 0001h 00xxh 000xh 0000h 000xh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
Device Geometry Definition
Description
Device Size = 2N byte 1A = 512 Mb, 19 = 256 Mb, 18 = 128 Mb Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device (01h = uniform device, 02h = boot device) Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 00FFh, 001h, 0000h, 0002h = 512 Mb 00FFh, 0000h, 0000h, 0002h = 256 Mb 007Fh, 0000h, 0000h, 0002h = 128 Mb
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
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Table 11. Primary Vendor-Specific Extended Query
Addresses (x16) 40h 41h 42h 43h 44h 45h Data 0050h 0052h 0049h 0031h 0033h 0010h Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Process Technology (Bits 7-2) 0100b = 110 nm MirrorBit 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 0002h 0001h 0000h 0008h 0000h 0000h 0002h 00B5h 00C5h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 0008h = Advanced Sector Protection Simultaneous Operation 00 = Not Supported, X = Number of Sectors in Bank Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV WP# Protection 4Fh 00xxh 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top WP# protect Program Suspend 00h = Not Supported, 01h = Supported
50h
0001h
Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations. Table 12 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams.
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Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any nonerase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations-"AC Characteristics" section provides the read parameters, and Figure 11 shows the timing diagram.
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 12 shows the address and data requirements. This method is an alternative to that shown in Table 5, which is intended for PROM programmers and requires VID on address pin A9. The autoselect command sequence may be written to an
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address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: A read cycle at address XX00h returns the manufacturer code. Three read cycles at addresses 01h, 0Eh, and 0Fh return the device code. A read cycle to an address containing a sector address (SA), and the address 02h on A7-A0 in word mode returns 01h if the sector is protected, or 00h if it is unprotected. The system must write the reset command to return to the read mode (or erasesuspend-read mode if the device was previously in Erase Suspend).
Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence
The Secured Silicon Sector region provides a secured data area containing an 8word/16-byte random Electronic Serial Number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation. Table 12 shows the address and data requirements for both command sequences. See also "Secured Silicon Sector Flash Memory Region" for further information. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 12 shows the address and data requirements for the word program command sequence. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence of address locations and across sector boundaries. Programming to the same word address multiple times without intervening erases (incremental bit programming) requires a modified programming method. For such application requirements, please contact your
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local Spansion representative. Word programming is supported for backward compatibility with existing Flash driver software and for occasional writing of individual words. Use of Write Buffer Programming is strongly recommended for general programming use when more than a few words are to be programmed. The effective word programming time using Write Buffer Programming is much shorter than the single word programming time. Any word cannot be programmed from "0" back to a "1." Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1."
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 12 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (See Table 12).
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will program 6 unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits AMAX-A4. All subsequent address/ data pairs must fall within the selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort.)
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Note that if a Write Buffer address location is loaded multiple times, the address/ data pair counter will be decremented for every data load operation. The host system must therefore account for loading a write-buffer location more than once. The counter decrements for each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: Load a value that is greater than the page buffer size during the Number of Locations to Program step. Write to an address in a sector different than the one specified during the Write-Buffer-Load command. Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode. Write buffer programming is allowed in any sequence. Note that the Secured Silicon sector, autoselect, and CFI functions are unavailable when a program operation is in progress. This flash device is capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. For applications requiring incremental bit programming, a modified programming method is required, please contact your local Spansion representative. Any bit in a write buffer address range cannot be programmed from "0" back to a "1." Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1."
Accelerated Program
The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not
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be at VHH for operations other than accelerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at VIH. Figure 2 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations-"AC Characteristics" section for parameters, and Figure 14 for timing diagrams.
Write "Write to Buffer" command and Sector Address
Write number of addresses to program minus 1(WC) and Sector Address
Part of "Write to Buffer" Command Sequence
Write first address/data
Yes
WC = 0 ? No Abort Write to Buffer Operation? No Yes Write to buffer ABORTED. Must write "Write-to-buffer Abort Reset" command sequence to return to read mode. Write to a different sector address
(Note 1)
Write next address/data pair
WC = WC - 1
Write program buffer to flash sector address
Notes:
1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page. 2. DQ7 may change simultaneously with DQ5. Therefore, DQ7 should be verified. 3. If this flowchart location was reached because DQ5= "1", then the device FAILED. If this flowchart location was reached because DQ1= "1", then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin another operation. If DQ1=1, write the WriteBuffer-Programming-Abort-Reset command. if DQ5=1, write the Reset command. 4. See Table 12 for command sequences required for write buffer programming.
Read DQ15 - DQ0 at Last Loaded Address
DQ7 = Data? No No DQ1 = 1? Yes DQ5 = 1? Yes Read DQ15 - DQ0 with address = Last Loaded Address No
Yes
(Note 2)
DQ7 = Data? No
Yes
(Note 3)
FAIL or ABORT
PASS
Figure 1. Write Buffer Programming Operation
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START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
Verify Data?
No
Yes No
Increment Address
Last Address?
Yes Programming Completed
Note: See Table 12 for program command sequence.
Figure 2.
Program Operation
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the program operation within 15 s maximum (5s typical) and updates the status bits. Addresses are not required when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area (One-time Program area), then user must use the proper command sequences to enter and exit this region. Note that the Secured Silicon Sector autoselect, and CFI functions are unavailable when program operation is in progress. The system may also write the autoselect command sequence when the device is in the Program Suspend mode. The system can read as many autoselect codes as required. When the device exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information.
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After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. The system must write the Program Resume command (address bits are don't care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device has resume programming.
Program Operation or Write-to-Buffer Sequence in Progress
Write address/data XXXh/B0h
Write Program Suspend Command Sequence Command is also valid for Erase-suspended-program operations
Wait 15 s
Read data as required
Autoselect and SecSi Sector read operations are also allowed Data cannot be read from erase- or program-suspended sectors
No
Done reading? Yes Write address/data XXXh/30h Write Program Resume Command Sequence
Device reverts to operation prior to Program Suspend
Figure 3.
Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 12 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to the Write Operation Status section for information on these status bits.
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Any commands written during the chip erase operation are ignored, including erase suspend commands. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase operation. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when an erase operation in is progress. Refer to the "Erase And Programming Performance" section on page 163 in the AC Characteristics section for parameters, and Figure 16 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 12 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise erasure may begin. Any sector erase address and command following the exceeded timeout may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when an erase operation in is progress. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 16 section for timing diagrams.
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START
Write Erase Command Sequence (Notes 1, 2)
Data Poll to Erasing Bank from System
Embedded Erase algorithm in progress
No
Data = FFh?
Yes Erasure Completed
Notes: 1. See Table 12 for program command sequence. 2. See the section on DQ3 for information on the sector erase timer.
Figure 4. Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a typical of 5 s (maximum of 20 s) to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. The system can determine the status of the pro-
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gram operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the "Autoselect Mode" section and "Autoselect Command Sequence" section on page 127 sections for details. To resume the sector erase operation, the system must write the Erase Resume command. The address of the erase-suspended sector is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. It is important to allow an interval of at least 5 ms between Erase Resume and Erase Suspend.
Lock Register Command Set Definitions
The Lock Register Command Set permits the user to one-time program the Secured Silicon Sector Protection Bit, Persistent Protection Mode Lock Bit, and Password Protection Mode Lock Bit. The Lock Register bits are all readable after an initial access delay. The Lock Register Command Set Entry command sequence must be issued prior to any of the following commands listed, to enable proper command execution. Note that issuing the Lock Register Command Set Entry command disables reads and writes for the flash memory. Lock Register Program Command Lock Register Read Command The Lock Register Command Set Exit command must be issued after the execution of the commands to reset the device to read mode. Otherwise the device will hang. If this happens, the flash device must be reset. Please refer to RESET# for more information. It is important to note that the device will be in either Persistent Protection mode or Password Protection mode depending on the mode selected prior to the device hang. For either the Secured Silicon Sector to be locked, or the device to be permanently set to the Persistent Protection Mode or the Password Protection Mode, the associated Lock Register bits must be programmed. Note that the Persistent Protection Mode Lock Bit and Password Protection Mode Lock Bit can never be programmed together at the same time. If so, the Lock Register Program operation will abort. The Lock Register Command Set Exit command must be initiated to reenable reads and writes to the main memory.
Password Protection Command Set Definitions
The Password Protection Command Set permits the user to program the 64-bit password, verify the programming of the 64-bit password, and then later unlock the device by issuing the valid 64-bit password. The Password Protection Command Set Entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. Note that issuing the Password Protection Command Set Entry command disabled reads and writes the main memory.
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Password Program Command Password Read Command Password Unlock Command The Password Program command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. There is no special addressing order required for programming the password. The password is programmed in 8-bit or 16-bit portions. Each portion requires a Password Program Command. Once the Password is written and verified, the Password Protection Mode Lock Bit in the "Lock Register" must be programmed in order to prevent verification. The Password Program command is only capable of programming "0"s. Programming a "1" after a cell is programmed as a "0" results in a time-out by the Embedded Program AlgorithmTM with the cell remaining as a "0". The password is all F's when shipped from the factory. All 64-bit password combinations are valid as a password. The Password Read command is used to verify the Password. The Password is verifiable only when the Password Protection Mode Lock Bit in the "Lock Register" is not programmed. If the Password Protection Mode Lock Bit in the "Lock Register" is programmed and the user attempts to read the Password, the device will always drive all F's onto the DQ databus. The lower two address bits (A1-A0) for word mode and (A1-A-1) for by byte mode are valid during the Password Read, Password Program, and Password Unlock commands. Writing a "1" to any other address bits (AMAX-A2) will abort the Password Read and Password Program commands. The Password Unlock command is used to clear the PPB Lock Bit to the "unfreeze state" so that the PPB bits can be modified. The exact password must be entered in order for the unlocking function to occur. This 64-bit Password Unlock command sequence will take at least 2 s to process each time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match the password. If another password unlock is issued before the 64-bit password check execution window is completed, the command will be ignored. If the wrong address or data is given during password unlock command cycle, the device may enter the write-tobuffer abort state. In order to exit the write-to-abort state, the write-tobuffer-abort-reset command must be given. Otherwise the device will hang. The Password Unlock function is accomplished by writing Password Unlock command and data to the device to perform the clearing of the PPB Lock Bit to the "unfreeze state". The password is 64 bits long. A1 and A0 are used for matching. Writing the Password Unlock command does not need to be address order specific. An example sequence is starting with the lower address A1-A0=00, followed by A1-A0=01, A1-A0=10, and A1-A0=11 if the device is configured to operate in word mode. Approximately 2 s is required for unlocking the device after the valid 64-bit password is given to the device. It is the responsibility of the microprocessor to keep track of the entering the portions of the 64-bit password with the Password Unlock command, the order, and when to read the PPB Lock bit to confirm successful password unlock. In order to re-lock the device into the Password Protection Mode, the PPB Lock Bit Set command can be re-issued.
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The Password Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. Otherwise the device will hang. Note that issuing the Password Protection Command Set Exit command reenables reads and writes for the main memory.
Non-Volatile Sector Protection Command Set Definitions
The Non-Volatile Sector Protection Command Set permits the user to program the Persistent Protection Bits (PPB bits), erase all of the Persistent Protection Bits (PPB bits), and read the logic state of the Persistent Protection Bits (PPB bits). The Non-Volatile Sector Protection Command Set Entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. Note that issuing the Non-Volatile Sector Protection Command Set Entry command disables reads and writes for the main memory. PPB Program Command The PPB Program command is used to program, or set, a given PPB bit. Each PPB bit is individually programmed (but is bulk erased with the other PPB bits). The specific sector address (A24-A16 for S29GL512N, A23-A16 for S29GL256N, A22A16 for S29GL128N) is written at the same time as the program command. If the PPB Lock Bit is set to the "freeze state", the PPB Program command will not execute and the command will time-out without programming the PPB bit. All PPB Erase Command The All PPB Erase command is used to erase all PPB bits in bulk. There is no means for individually erasing a specific PPB bit. Unlike the PPB program, no specific sector address is required. However, when the All PPB Erase command is issued, all Sector PPB bits are erased in parallel. If the PPB Lock Bit is set to "freeze state", the ALL PPB Erase command will not execute and the command will time-out without erasing the PPB bits. The device will preprogram all PPB bits prior to erasing when issuing the All PPB Erase command. Also note that the total number of PPB program/erase cycles has the same endurance as the flash memory array. PPB Status Read Command The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device. This requires an initial access time latency. The Non-Volatile Sector Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. Note that issuing the Non-Volatile Sector Protection Command Set Exit command re-enables reads and writes for the main memory.
Global Volatile Sector Protection Freeze Command Set
The Global Volatile Sector Protection Freeze Command Set permits the user to set the PPB Lock Bit and reading the logic state of the PPB Lock Bit. The Global Volatile Sector Protection Freeze Command Set Entry command sequence must be issued prior to any of the commands listed following to enable proper command execution.
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Reads and writes from the main memory are not allowed. PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock Bit to the "freeze state" if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set to the "freeze state", it cannot be cleared unless the device is taken through a power-on clear (for Persistent Protection Mode) or the Password Unlock command is executed (for Password Protection Mode). If the Password Protection Mode Lock Bit is programmed, the PPB Lock Bit status is reflected as set to the "freeze state", even after a power-on reset cycle. PPB Lock Bit Status Read Command The programming state of the PPB Lock Bit can be verified by executing a PPB Lock Bit Status Read command to the device. The Global Volatile Sector Protection Freeze Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode.
Volatile Sector Protection Command Set
The Volatile Sector Protection Command Set permits the user to set the Dynamic Protection Bit (DYB) to the "protected state", clear the Dynamic Protection Bit (DYB) to the "unprotected state", and read the logic state of the Dynamic Protection Bit (DYB). The Volatile Sector Protection Command Set Entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. Note that issuing the Volatile Sector Protection Command Set Entry command disables reads and writes from main memory. DYB Set Command DYB Clear Command The DYB Set and DYB Clear commands are used to protect or unprotect a DYB for a given sector. The high order address bits are issued at the same time as the code 00h or 01h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYB bits are modifiable at any time, regardless of the state of the PPB bit or PPB Lock Bit. The DYB bits are cleared to the "unprotected state" at power-up or hardware reset.
--DYB Status Read Command
The programming state of the DYB bit for a given sector can be verified by writing a DYB Status Read command to the device. This requires an initial access delay. The Volatile Sector Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. Note that issuing the Volatile Sector Protection Command Set Exit command re-enables reads and writes to the main memory.
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Secured Silicon Sector Entry Command
The Secured Silicon Sector Entry command allows the following commands to be executed Read from Secured Silicon Sector Program to Secured Silicon Sector Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command has to be issued to exit Secured Silicon Sector Mode.
Secured Silicon Sector Exit Command
The Secured Silicon Sector Exit command may be issued to exit the Secured Silicon Sector Mode.
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Command Definitions
Table 12. S29GL512N, S29GL256N, S29GL128N Command Definitions, x16
Command (Notes) Cycles Bus Cycles (Notes 2-5) First Addr RA XXX 555 555 Data RD F0 AA AA 2AA 2AA 55 55 555 555 90 90 X00 X01 (SA) X02 X03 01 227E XX00 XX01 Note 10 X0E Note 17 X0F Note 17 Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data
Read (6) Reset (7) Manufacturer ID Autoselect (Note 8) Device ID
1 1 4 4
Sector Protect Verify
4
555
AA
2AA
55
555
90
Secure Device Verify (9)
4 1 4 3 1 3 3 2 2 2 2 6 6 1 1
555 55 555 555 SA 555 555 XXX XXX XXX XXX 555 555 XXX XXX
AA 98 AA AA 29 AA AA A0 80 80 90 AA AA B0 30
2AA
55
555
90
CFI Query (11) Program Write to Buffer Program Buffer to Flash (confirm) Write-to-Buffer-Abort Reset (16) Unlock Bypass Unlock Bypass Program (12) Unlock Bypass Sector Erase (12) Unlock Bypass Chip Erase (12) Unlock Bypass Reset (13) Chip Erase Sector Erase Erase Suspend/Program Suspend (14) Erase Resume/Program Resume (15)
2AA 2AA
55 55
555 SA
A0 25
PA SA
PD WC PA PD WBL PD
2AA 2AA PA SA XXX XXX 2AA 2AA
55 55 PD 30 10 00 55 55
555 555
F0 20
555 555
80 80
555 555
AA AA
2AA 2AA
55 55
555 SA
10 30
Sector Command Definitions
Secured Silicon SEctor Secured Silicon Sector Entry 3 555 AA 2AA 55 555 88
Secured Silicon Sector Exit (18)
4
555
AA
2AA
55
555
90
XX
00
Lock Register Command Set Definitions
Lock Register Lock Register Command Set Entry Lock Register Bits Program (22) Lock Register Bits Read (22) Lock Register Command Set Exit (18, 23) 3 2 1 2 555 XXX 00 XXX AA A0 Data 90 XXX 00 2AA XXX 55 Data 555 40
Password Protection Command Set Definitions
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Command (Notes)
Cycles
Bus Cycles (Notes 2-5) First Addr 555 XXX XXX 00 00 Data AA A0 PWD 0 25 29 90 XXX 00 Second Addr 2AA PWA x 01 00 Data 55 PWD x PWD 1 03 02 00 PWD 2 PWD 0 03 01 PWD 3 PWD 1 02 PWD 2 03 PWD 3 Third Addr 555 Data 60 Fourth Addr Data Fifth Addr Data Sixth Addr Data
Password Protection Command Set Entry Password Program (20) Password Password Read (19)
3 2 4
Password Unlock (19)
7
Password Protection Command Set Exit (18, 23)
2
XXX
Non-Volatile Sector Protection Command Set Definitions
Nonvolatile Sector Protection Command Set Entry PPB Program (24, 25) PPB All PPB Erase PPB Status Read (25) Non-Volatile Sector Protection Command Set Exit (18) 3 2 2 1 2 555 XXX XXX SA XXX AA A0 80 RD (0) 90 XXX 00 2AA SA 00 55 00 30 555 C0
Global Non-Volatile Sector Protection Freeze Command Set Definitions
Global Non-Volatile Sector Protection Freeze Command Set Entry PPB Lock Bit PPB Lock Bit Set (25) PPB Lock Status Read (25) Global Non-Volatile Sector Protection Freeze Command Set Exit (18) 3 2 1 2 555 XXX XXX XXX AA A0 RD (0) 90 XXX 00 2AA XXX 55 00 555 50
Volatile Sector Protection Command Set Definitions
Volatile Sector Protection Command Set Entry DYB Set (24, 25) DYB DYB Clear (25) DYB Status Read (25) Volatile Sector Protection Command Set Exit (18) 3 2 2 1 2 555 XXX XXX SA XXX AA A0 A0 RD (0) 90 XXX 00 2AA SA SA 55 00 01 555 E0
Legend: X = Don't care RA = Address of the memory to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax-A16 uniquely select any sector. WBL = Write Buffer Location. The address must be within the same write buffer page as PA.
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WC = Word Count is the number of write buffer locations to load minus 1. PWD = Password PWDx = Password word0, word1, word2, and word3. DATA = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit, PD(1) = Persistent Protection Mode Lock Bit, PD(2) = Password Protection Mode Lock Bit. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle, and the 4th, 5th, and 6th cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15-DQ8 are don't cares for unlock and command cycles. 5. Address bits AMAX:A16 are don't cares for unlock and command cycles, unless SA or PA required. (AMAX is the Highest Address pin.). 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 8. The fourth, fifth, and sixth cycle of the autoselect command sequence is a read cycle. 9. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more information. This is same as PPB Status Read except that the protect and unprotect statuses are inverted here. 10. The data value for DQ7 is "1" for a serialized and protected OTP region and "0" for an unserialized and unprotected Secured Silicon Sector region. See "Secured Silicon Sector Flash Memory Region" for more information. For S29GLxxxNH: XX18h/18h = Not Factory Locked. XX98h/98h = Factory Locked. For S29GLxxxNL: XX08h/08h = Not Factory Locked. XX88h/88h = Factory Locked. 11. Command is valid when device is ready to read array data or when device is in autoselect mode. 12. The Unlock-Bypass command is required prior to the Unlock-Bypass-Program command. 13. The Unlock-Bypass-Reset command is required to return to reading array data when the device is in the unlock bypass mode. 14. The system may read and program/program suspend in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 15. The Erase Resume/Program Resume command is valid only during the Erase Suspend/Program Suspend modes. 16. Issue this command sequence to return to READ mode after detecting device is in a Write-to-Buffer-Abort state. NOTE: the full command sequence is required if resetting out of ABORT while using Unlock Bypass Mode. 17. S29GL512NH/L = 2223h/23h, 2201h/01h; S29GL256NH/L = 2222h/22h, 2201h/01h; S29GL128NH/L = 2221h/21h, 2201h/ 01h. 18. The Exit command returns the device to reading the array. 19. Note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. 20. For PWDx, only one portion of the password can be programmed per each "A0" command. 21. The All PPB Erase command embeds programming of all PPB bits before erasure. 22. All Lock Register bits are one-time programmable. Note that the program state = "0" and the erase state = "1". Also note that of both the Persistent Protection Mode Lock Bit and the Password Protection Mode Lock Bit cannot be programmed at the same time or the Lock Register Bits Program operation will abort and return the device to read mode. Lock Register bits that are reserved for future use will default to "1's". The Lock Register is shipped out as "FFFF's" before Lock Register Bit program execution. 23. If any of the Entry command was initiated, an Exit command must be issued to reset the device into read mode. Otherwise the device will hang. 24. If ACC = VHH, sector protection will match when ACC = VIH 25. Protected State = "00h", Unprotected State = "01h".
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Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 13 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. Note that all Write Operation Status DQ bits are valid only after 4 s delay.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then the device returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. Valid data on DQ0-DQ7 will appear on successive read cycles. Table 13 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm. Figure 17 in the AC Characteristics section shows the Data# Polling timing diagram.
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START
Read DQ15-DQ0 Addr = VA
DQ7 = Data?
Yes
No No
DQ5 = 1
Yes Read DQ15-DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
Figure 5. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 13 shows the outputs for RY/BY#.
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DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 13 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm. Figure 18 in the "AC Characteristics" section shows the toggle bit timing diagrams. Figure 19 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.
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START
Read DQ7-DQ0
Read DQ7-DQ0
Toggle Bit = Toggle? Yes
No
No
DQ5 = 1?
Yes
Read DQ7-DQ0 Twice
Toggle Bit = Toggle? Yes Program/Erase Operation Not Complete, Write Reset Command
No
Program/Erase Operation Complete
Note: The system should recheck the toggle bit even if DQ5 = "1" because the toggle bit may stop toggling as DQ5 changes to "1." See the subsections on DQ6 and DQ2 for more information.
Figure 6. Toggle Bit Algorithm
DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the
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read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 13 to compare outputs for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section "DQ2: Toggle Bit II" explains the algorithm. See also the RY/BY#: Ready/Busy# subsection. Figure 18 shows the toggle bit timing diagram. Figure 19 shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 and Figure 19 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed. The device may output a "1" on DQ5 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a "1." In all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure,
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the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a "0" to a "1." If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 13 shows the status of DQ3 relative to the other status bits.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a "1". The system must issue the Write-to-Buffer-AbortReset command sequence to return the device to reading array data. See Write Buffer section for more details.
Table 13.
Status Standard Mode Program Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm ProgramSuspend Read Program-Suspended Sector Non-Program Suspended Sector Erase-Suspended Sector Non-Erase Suspended Sector
Write Operation Status
DQ6 Toggle Toggle DQ5 (Note 1) 0 0 DQ3 N/A 1 DQ2 (Note 2) No toggle Toggle DQ1 0 N/A RY/ BY# 0 0 1 1 N/A Data Toggle N/A 1 1 N/A N/A N/A N/A N/A N/A N/A 0 1 0 0 0
DQ7 (Note 2) DQ7# 0
Invalid (not allowed) Data 1 No toggle 0
Erase Suspend Mode
EraseSuspend Read
Erase-Suspend-Program (Embedded Program) Write-toBuffer
Notes:
DQ7# DQ7# DQ7#
Toggle Toggle Toggle
0 0 0
Busy (Note 3) Abort (Note 4)
1. DQ5 switches to `1' when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location. 4. DQ1 switches to `1' when the device has aborted the write-to-buffer operation.
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Absolute Maximum Ratings
Storage Temperature, Plastic Packages . . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . -65C to +125C Voltage with Respect to Ground: VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to +4.0 V VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to +4.0 V A9, OE#, and ACC (Note 2) . . . . . . . . . . . . . . . . . . . -0.5 V to +12.5 V All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . .-0.5 V to VCC + 0.5V Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/Os is -0.5 V. During voltage transitions, inputs or I/Os may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pins A9, OE#, and ACC is -0.5 V. During voltage transitions, A9, OE#, and ACC may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin A9, OE#, and ACC is +12.5 V which may overshoot to +14.0V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
20 ns +0.8 V -0.5 V -2.0 V 20 ns
20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns
20 ns
20 ns
Figure 7. Maximum Negative Overshoot Waveform
Figure 8. Maximum Positive Overshoot Waveform
Operating Ranges
Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to +3.6 V or +3.0V to 3.6V VIO (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.65V to 1.95V or VCC
Notes: 1. Operating ranges define those limits between which the functionality of the device is guaranteed. 2. See "Product Selector Guide" section on page 80.
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DC Characteristics
CMOS Compatible-S29GL128N, S29GL256N, S29GL512N
Parameter Symbol ILI ILIT ILO Parameter Description (Notes) Input Load Current (1) A9 Input Load Current Output Leakage Current Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC max CE# = VIL, OE# = VIH, VCC = VCCmax, f = 5 MHz ICC1 VCC Active Read Current (1) CE# = VIL, OE# = VIH, VCC = VCCmax, f = 10 MHz CE# = VIL, OE# = VIH, VCC = VCCmax f = 10 MHz CE# = VIL, OE# = VIH, VCC = VCCmax, f=33 MHz 30 60 1 5 50 1 Min Typ Max WP/ACC: 2.0 Others: 1.0 35 1.0 50 90 10 mA 20 80 5 mA mA Unit
A A A
mA
ICC2
VCC Intra-Page Read Current (1)
ICC3 ICC4
VCC Active Erase/Program Current (2, 3) CE# = VIL, OE# = VIH, VCC = VCCmax VCC Standby Current CE#, RESET# = VSS 0.3 V, OE# = VIH, VCC = VCCmax VIL = VSS + 0.3 V/0.1V VCC = VCCmax; VIL = VSS + 0.3 V/-0.1V, RESET# = VSS 0.3 V VCC = VCCmax VIH = VCC 0.3 V, VIL = VSS + 0.3 V/-0.1V, WP#/ACC = VIH CE# = VIL, OE# = VIH, VCC = VCCmax, WP#/ACC = VIH WP#/ACC pin VCC pin -0.1 0.7 x VIO VCC = 2.7 -3.6 V VCC = 2.7 -3.6 V IOL = 100 A IOH = -100 A 0.85 x VIO 2.3 11.5 11.5
ICC5
VCC Reset Current
1
5
A
ICC6
Automatic Sleep Mode (4)
1
5
A
IACC
ACC Accelerated Program Current
10 50
20 80 0.3 x VIO VIO + 0.3 12.5 12.5 0.15 x VIO
mA
VIL VIH VHH VID VOL VOH VLKO
Input Low Voltage (5) Input High Voltage (5) Voltage for ACC Erase/Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage (5) Output High Voltage (5) Low VCC Lock-Out Voltage (3)
V V V V V V
2.5
V
Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Erase or Embedded Program or Write Buffer Programming is in progress. 3. Not 100% tested. 4. Automatic sleep mode enables the lower power mode when addresses remain stable tor tACC + 30 ns. 5. VIO = 1.65-1.95 V or 2.7-3.6 V 6. VCC = 3 V and VIO = 3V or 1.8V. When VIO is at 1.8V, I/O pins cannot operate at 3V.
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Test Conditions
Table 14.
3.3 V
Test Specifications
All Speeds 1 TTL gate 30 5 0.0-VIO 0.5VIO 0.5 VIO pF ns V V V Unit
Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels (See Note) Output timing measurement reference levels
Device Under Test CL 6.2 k
2.7 k
Note: Diodes are IN3064 or equivalent.
Figure 9.
Test Setup
Note: If VIO < VCC, the reference level is 0.5 VIO.
Key to Switching Waveforms
Waveform Inputs Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) Outputs
VIO 0.0 V
Input
0.5 VIO
Measurement Level
0.5 VIO V
Output
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.
Figure 10.
Input Waveforms and Measurement Levels
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AC Characteristics
Read-Only Operations-S29GL128N, S29GL256N, S29GL512N
Parameter JEDEC tAVAV Std. tRC Description Read Cycle Time Address to Output Delay (Note 2) Chip Enable to Output Delay (Note 3) Test Setup VIO = VCC = 3 V VIO = 1.8 V, VCC = 3 V VIO = VCC = 3 V VIO = 1.8 V, VCC = 3 V VIO = VCC = 3 V VIO = 1.8 V, VCC = 3 V Min Speed Options 90 90 100 110 110 Unit 100 110 110 90 100 110 110 90 100 110 110 25 25 25 25 20 20 0 0 10 35 25 35 30 35 ns
tAVQV
tACC
Max
ns
tELQV
tCE
Max Max Max Max Max Min Min Min Min
ns ns ns ns ns ns ns ns ns
tPACC Page Access Time tGLQV tEHQZ tGHQZ tAXQX tOE tDF tDF tOH Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Output Enable Hold Time (Note 1) Read Toggle and Data# Polling
tOEH tCEH
Notes:
Chip Enable Hold Time Read
1. Not 100% tested. 2. CE#, OE# = VIL 3. OE# = VIL 4. See Figure 9 and Table 14 for test specifications. 5. Unless otherwise indicated, AC specifications for 90 ns, 100 ns, and 110 ns speed options are tested with VIO = VCC = 3 V. AC specifications for 110 ns speed options are tested with VIO = 1.8 V and VCC = 3.0 V.
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AC Characteristics
tRC Addresses CE# Addresses Stable tACC tCEH tRH tRH OE# tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tOE tDF
0V
Figure 11.
Read Operation Timings
Amax-A2
Same Page
A2-A0*
Aa
tACC
Ab
tPACC
Ac
tPACC tPACC
Ad
Data Bus CE# OE#
Qa
Qb
Qc
Qd
Notes: 1. Figure shows word mode.
Figure 12. Page Read Timings
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AC Characteristics
Hardware Reset (RESET#)
Parameter JEDEC Std. tReady tReady tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Max Max Min Min Min Min Speed (Note 2) 20 500 500 50 20 0 Unit ns ns ns ns s ns
Notes: 1. Not 100% tested. If ramp rate is equal to or faster than 1V/100s with a falling edge of the RESET# pin initiated, the RESET# pin needs to be held low only for 100s for power-up. 2. Next generation devices may have different reset speeds.
RY/BY#
CE#, OE# tRH RESET# tRP tReady
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# tRB CE#, OE#
RESET# tRP tRH
Figure 13.
Reset Timings
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AC Characteristics
Erase and Program Operations-S29GL128N, S29GL256N, S29GL512N
Parameter JEDEC tAVAV tAVWL Std. tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tCEPH tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tCS tCH tWP tWPH Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time CE# High during toggle bit polling Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Write Buffer Program Operation (Notes 2, 3) Effective Write Buffer Program Operation (Notes 2, 4) tWHWH1 tWHWH1 Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Program Operation (Note 2) Accelerated Programming Operation (Note 2) tWHWH2 tWHWH2 Sector Erase Operation (Note 2) tVHH tVCS tBUSY VHH Rise and Fall Time (Note 1) VCC Setup Time (Note 1) Erase/Program Valid to RY/BY# Delay Per Word Per Word Word Word Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ Typ Typ Min Min Min 90 90 Speed Options 100 100 0 15 45 0 45 0 20 20 0 0 0 35 30 240 15 13.5 60 54 0.5 250 50 90 ns ns ns ns ns ns s s s s s sec ns s ns 110 110 110 110 Unit ns ns ns ns ns ns ns
Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. 3. For 1-16 words/1-32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. Unless otherwise indicated, AC specifications for 90 ns, 100 ns, and 110 ns speed options are tested with VIO = VCC = 3 V. AC specifications for 110 ns speed options are tested with VIO = 1.8 V and VCC = 3.0 V.
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AC Characteristics
Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# Status DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles)
tCH
A0h
VCC tVCS
Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode.
Figure 14.
Program Operation Timings
VHH
ACC
VIL or VIH tVHH tVHH
VIL or VIH
Figure 15.
Notes: 1. Not 100% tested. 2. CE#, OE# = VIL 3. OE# = VIL
Accelerated Program Timing Diagram
4. See Figure 9 and Table 14 for test specifications.
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AC Characteristics
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA
555h for chip erase
Read Status Data
VA tAH
VA
CE#
OE# tWP WE# tCS tDS
tCH
tWPH
tWHWH2
tDH Data 55h 30h
10 for Chip Erase In Progress Complete
tBUSY RY/BY# tVCS VCC
tRB
Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status". 2. These waveforms are for the word mode.
Figure 16.
Chip/Sector Erase Operation Timings
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AC Characteristics
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7
High Z
VA
VA
tOE tDF
Complement
Complement
True
Valid Data
High Z
DQ6-DQ0 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note:
1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. 2. tOE for data polling is 45 ns when VIO = 1.65 to 2.7 V and is 35 ns when VIO = 2.7 to 3.6 V
Figure 17. Data# Polling Timings (During Embedded Algorithms)
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AC Characteristics
tAHT Addresses tAHT tASO CE# tOEH WE# tOEPH OE# tDH DQ2 and DQ6 Valid Data
Valid Status
tAS
tCEPH
tOE
Valid Status Valid Status
Valid Data
(first read) RY/BY#
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle
Figure 18. Toggle Bit Timings (During Embedded Algorithms)
Enter Embedded Erasing WE#
Erase Suspend Erase
Enter Erase Suspend Program
Erase Resume Erase Erase Complete
Erase Suspend Read
Erase Erase Suspend Suspend Read Program
DQ6
DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
Figure 19.
DQ2 vs. DQ6
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AC Characteristics
Alternate CE# Controlled Erase and Program OperationsS29GL128N, S29GL256N, S29GL512N
Parameter JEDEC tAVAV tAVWL Std. tWC tAS TASO tELAX tAH tAHT tDVEH tEHDX tDS tDH tCEPH tOEPH tGHEL tWLEL tEHWH tELEH tEHEL tGHEL tWS tWH tCP tCPH Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time CE# High during toggle bit polling OE# High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Write Buffer Program Operation (Notes 2, 3) Effective Write Buffer Program Operation (Notes 2, 4) tWHWH1 tWHWH1 Effective Accelerated Write Buffer Program Operation (Notes 2, 4) Program Operation (Note 2) Accelerated Programming Operation (Note 2) tWHWH2 tWHWH2 Sector Erase Operation (Note 2)
Notes: 1. Not 100% tested. 2. See the "AC Characteristics" section for more information. 3. For 1-16 words/1-32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. Unless otherwise indicated, AC specifications for 90 ns, 100ns, and 110 ns speed options are tested with VIO = VCC = 3 V. AC specifications for 110 ns speed options are tested with VIO = 1.8 V and VCC = 3.0 V.
Speed Options 90 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ 90 100 100 0 15 45 0 45 0 20 20 0 0 0 35 30 240 110 110 110 110 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
Per Word
Typ
15
s
Per Word Word Word
Typ Typ Typ Typ
13.5 60 54 0.5
s s s sec
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AC Characteristics
555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode.
Figure 20. Alternate CE# Controlled Write (Erase/Program) Operation Timings
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Erase And Programming Performance
Parameter Sector Erase Time S29GL128N Chip Erase Time S29GL256N S29GL512N Total Write Buffer Programming Time (Note 3) Total Accelerated Effective Write Buffer Programming Time (Note 3) S29GL128N Chip Program Time S29GL256N S29GL512N Typ (Note 1) 0.5 64 128 256 240 Max (Note 2) 3.5 256 512 1024 s sec Unit sec Excludes 00h programming prior to erasure (Note 5) Comments
200 123 246 492
s
Excludes system level overhead (Note 6)
sec
Notes: 1. Typical program and erase times assume the following conditions: 25C, 3.0 V VCC, 10,000 cycles, checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 3.0 V, 100,000 cycles. 3. Effective write buffer specification is based upon a 16-word write buffer operation. 4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 12 for further information on command definitions.
TSOP Pin and BGA Package Capacitance
Parameter Symbol CIN Parameter Description Input Capacitance Test Setup VIN = 0 TSOP BGA TSOP BGA TSOP BGA Typ 6 4.2 8.5 5.4 7.5 3.9 Max 7.5 5.0 12 6.5 9 4.7 Unit pF pF pF pF pF pF
COUT
Output Capacitance
VOUT = 0
CIN2
Control Pin Capacitance
VIN = 0
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
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Information
pSRAM Type 2
16Mb (1Mb Word x 16-bit) 32Mb (2Mb Word x 16-bit) 64Mb (4Mb Word x 16-bit) Features
Process Technology: CMOS Organization: x16 bit Power Supply Voltage: 2.7~3.1V Three State Outputs Compatible with Low Power SRAM
Product Information
Density 16Mb 16Mb 32Mb 32Mb 64Mb 64Mb VCC Range 2.7-3.1V 2.7-3.1V 2.7-3.1V 2.7-3.1V 2.7-3.1V 2.7-3.1V Standby (ISB1, Max.) 80 A 80 A 100 A 100 A TBD TBD Operating (ICC2, Max.) 30 mA 35 mA 35 mA 40 mA TBD TBD Mode Dual CS Dual CS and Page Mode Dual CS Dual CS and Page Mode Dual CS Dual CS and Page Mode
Pin Description
Pin Name CS1#, CS2 OE# WE# LB#, UB# A0-A19 (16M) A0-A20 (32M) A0-A21 (64M) I/O0-I/O15 VCC/VCCQ VSS/VSSQ NC DNU Chip Select Output Enable Write Enable Lower/Upper Byte Enable Address Inputs Data Inputs/Outputs Power Supply Ground Not Connection Do Not Use Description I/O I I I I I I/O -- -- -- --
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Information
Power Up Sequence
1. 2. Apply power. Maintain stable power (VCC min.=2.7V) for a minimum 200 s with CS1#=high or CS2=low.
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Timing Diagrams
Power Up
VCC(Min)
VCC Min.200 s
CS1#
CS2
Power Up Mode
~~ ~~
~ ~
~ ~
Normal Operation
Figure 21. Power Up 1 (CS1# Controlled)
Notes:
1. After VCC reaches VCC(Min.), wait 200 s with CS1# high. Then the device gets into the normal operation.
VCC
CS1#
Power Up Mode
~ ~
CS2
~~ ~~
~ ~
VCC(Min)
Min. 200s
Normal Operation
Figure 22. Power Up 2 (CS2 Controlled)
Notes:
1. After VCC reaches VCC(Min.), wait 200 s with CS2 low. Then the device gets into the normal operation.
Functional Description
Mode Deselected Deselected Deselected Output Disabled Outputs Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write CS1# H X X L L L L L L L L CS2 X L X H H H H H H H H OE# X X X H H L L L X X X WE# X X X H H H H H L L L LB# X X H L X L H L L H L UB# X X H X L H L L H L L I/O1-8 High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN I/O9-16 High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Power Standby Standby Standby Active Active Active Active Active Active Active Active
Legend:X = Don't care (must be low or high state).
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Absolute Maximum Ratings
Item Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Power Dissipation Operating Temperature
Notes:
1. Stresses greater than those listed under "Absolute Maximum Ratings" section may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability.
Symbol VIN , VOUT VCC PD TA
Ratings -0.2 to VCC+0.3V -0.2 to 3.6V 1.0 -40 to 85
Unit V V W C
DC Recommended Operating Conditions
Symbol VCC VSS VIH VIL
Notes:
1. TA=-40 to 85C, otherwise specified. 2. Overshoot: VCC+1.0V in case of pulse width 20ns. 3. Undershoot: -1.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested.
Parameter Power Supply Voltage Ground Input High Voltage Input Low Voltage
Min 2.7 0 2.2 -0.2 (Note 3)
Typ 2.9 0 -- --
Max 3.1 0 VCC + 0.3 (Note 2) 0.6
Unit
V
Capacitance (Ta = 25C, f = 1 MHz)
Symbol CIN COIO Parameter Input Capacitance Input/Output Capacitance Test Condition VIN = 0V VOUT = 0V Min -- -- Max 8 10 Unit pF pF
Note: This parameter is sampled periodically and is not 100% tested.
DC and Operating Characteristics
Common
Item Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Symbol ILI ILO VOL VOH Test Conditions VIN=VSS to VCC CS1#=VIH or CS2=VIL or OE#=VIH or WE#=VIL or LB#=UB#=VIH, VIO=VSS to VCC IOL=2.1mA IOH=-1.0mA Min -1 -1 -- 2.4 Typ -- -- -- -- Max 1 1 0.4 -- Unit A A V V
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16M pSRAM
Item Symbol ICC1 Average Operating Current ICC2 Page Test Conditions Cycle time=1s, 100% duty, IIO=0mA, CS1#0.2V, LB#0.2V and/or UB#0.2V, CS2VCC-0.2V, VIN0.2V or VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN=VIH or VIL Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL Other inputs=0-VCC 1. CS1# VCC - 0.2, CS2 VCC - 0.2V (CS1# controlled) or 2. 0V CS2 0.2V (CS2 controlled)
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from the time when standby mode is set up.
Min Typ Max Unit -- -- 7 mA
Async
--
--
30
mA
35
mA
Standby Current (CMOS)
ISB1 (Note 1)
--
--
80
mA
32M pSRAM
Item Symbol ICC1 Average Operating Current ICC2 Page Test Conditions Cycle time=1s, 100% duty, IIO=0mA, CS1#0.2V, LB#0.2V and/or UB#0.2V, CS2VCC-0.2V, VIN0.2V or VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN=VIH or VIL Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL Other inputs=0-VCC 1. CS1# VCC - 0.2, CS2 VCC - 0.2V (CS1# controlled) or 2. 0V CS2 0.2V (CS2 controlled)
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from the time when standby mode is set up.
Min Typ Max Unit -- -- 7 mA
Async
--
--
35
mA
40
mA
Standby Current (CMOS)
ISB1 (Note 1)
--
--
100 mA
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64M pSRAM
Item Symbol ICC1 Average Operating Current ICC2 Page Test Conditions Cycle time=1s, 100% duty, IIO=0mA, CS1#0.2V, LB#0.2V and/or UB#0.2V, CS2VCC-0.2V, VIN0.2V or VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN=VIH or VIL Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL Other inputs=0-VCC 1. CS1# VCC - 0.2, CS2 VCC - 0.2V (CS1# controlled) or 2. 0V CS2 0.2V (CS2 controlled)
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from the time when standby mode is set up.
Min Typ Max Unit -- -- TBD mA
Async
--
--
TBD
mA
TBD
mA
Standby Current (CMOS)
ISB1 (Note 1)
--
--
TBD
mA
AC Operating Conditions
Test Conditions (Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See Figure 23): CL=50pF
Dout
CL
Figure 23. Output Load
Note: Including scope and jig capacitance.
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ACC Characteristics (Ta = -40C to 85C, VCC = 2.7 to 3.1 V)
Speed Bins 70ns Symbol tRC tAA tCO tOE tBA tLZ Read tBLZ tOLZ tHZ tBHZ tOHZ tOH tPC tPA tWC tCW tAS tAW Write tBW tWP tWR tWHZ tDW tDH tOW
Notes:
1. tWP (min)=70ns for continuous write operation over 50 times.
Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output UB#, LB# Access Time Chip Select to Low-Z Output UB#, LB# Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB#, LB# Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Page Cycle Time Page Access Time Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write UB#, LB# Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z
Min 70 -- -- -- -- 10 10 5 0 0 0 5 25 -- 70 60 0 60 60 55 (Note 1) 0 0 30 0 5
Max -- 70 70 35 70 -- -- -- 25 25 25 -- -- 20 -- -- -- -- -- -- -- 25 -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Timing Diagrams
Read Timings
tRC
Address
tOH tAA
Data Out
Previous Data Valid
Data Valid
Figure 24. Timing Waveform of Read Cycle(1)
Notes:
1. Address Controlled, CS1#=OE#=VIL, CS2=WE#=VIH, UB# and/or LB#=VIL.
tRC
Address
tAA tOH tCO
CS1#
CS2
tHZ
UB#, LB#
tBA tBHZ
OE#
tOLZ tBLZ tLZ
tOE tOHZ
Data out
High-Z
Data Valid
Figure 25. Timing Waveform of Read Cycle(2)
Notes:
1. WE#=VIH.
Address
1)
Valid Address
A1~A0
Valid Address
Valid Address
Valid Address
Valid Address
tAA
tPC
CS1#
CS2
tCO
OE#
High Z tOE tPA
Data Valid Data Valid Dat a Valid Dat a Valid
tOHZ
DQ15~DQ0
Figure 26. Timing Waveform of Read Cycle(2)
Notes:
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Information
1. 16Mb: A2 ~ A19, 32Mb: A2 ~ A20, 64Mb: A2 ~ A21.
tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. tOE(max) is met only when OE# becomes enabled after tAA(max). If invalid address signals shorter than min. T.RC are continuously repeated for over 4s, the device needs a normal read timing (tRC) or needs to sustain standby state for min. tRC at least once in every 4s.
Write Timings
tWC Address tCW tWR
CS1#
CS2
tAW tBW tWP WE# tAS Data in High-Z tWHZ tDW Data Valid tOW tDH HighZ
UB#, LB#
Data out
Data Undefined
Figure 27. Write Cycle #1 (WE# Controlled)
tWC
Address
tAS tCW tAW tWR
CS1#
CS2
tBW tWP
UB#, LB#
WE#
tDW tDH
Data in Data out
Data Valid
High-Z
Figure 28. Write Cycle #2 (CS1# Controlled)
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tWC
Address
tAS tCW tAW tWR
CS1#
CS2
tBW tWP(1) WE# tDW Data in Data Valid tDH
UB#, LB#
Data out
High-Z
Figure 29. Timing Waveform of Write Cycle(3)(CS2 Controlled)
tWC Address
tCW tWR
CS1#
tAW
CS2
UB#, LB#
tAS tBW tWP
WE#
tDW tDH
Data in Data out High-Z
Data Valid
Figure 30. Timing Waveform of Write Cycle(4) (UB#, LB# Controlled)
Notes:
1. A write occurs during the overlap (tWP) of low CS1# and low WE#. A write begins when CS1# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS1# goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1# going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1# or WE# going high.
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pSRAM Type 6
2M Word by 16-bit Cmos Pseudo Static RAM (32M Density) 4M Word by 16-bit Cmos Pseudo Static RAM (64M Density) Features
Single power supply voltage of 2.6 to 3.3 V Direct TTL compatibility for all inputs and outputs Deep power-down mode: Memory cell data invalid Page operation mode: -- Page read operation by 8 words Logic compatible with SRAM R/W ( ) pin Standby current -- Standby = 70 A (32M) -- Standby = 100 A (64M) -- Deep power-down Standby = 5 A Access Times 32M 64M Access Time CE1# Access Time OE# Access Time Page Access Time 70 ns 70 ns 25 ns 30 ns
Pin Description
Pin Name A0 to A21 A0 to A2 I/O1 to I/O16 CE1# CE2 WE# OE# LB#,UB# VDD GND NC Address Inputs Page Address Inputs Data Inputs/Outputs Chip Enable Input Chip select Input Write Enable Input Output Enable Input Data Byte Control Inputs Power Supply Ground Not Connection Description
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Functional Description
Mode Read(Word) Read(Lower Byte) Read(Upper Byte) Write(Word) Write(Lower Byte) Write(Upper Byte) Outputs Disabled Standby Deep Power-down Standby CE1# L L L L L L L H H CE2 H H H H H H H H L OE# L L L X X X H X X WE# H H H L L L H X X LB# L L H L L H X X X UB# L H L L H L X X X Address X X X X X X X X X I/O1-8 DOUT DOUT High-Z DIN DIN Invalid High-Z High-Z High-Z I/O9-16 DOUT High-Z DOUT DIN Invalid DIN High-Z High-Z High-Z Power IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDSD
Legend:L = Low-level Input (VIL), H = High-level Input (VIH), X = VIL or VIH, High-Z = High Impedence.
Absolute Maximum Ratings
Symbol VDD VIN VOUT Topr Tstrg PD IOUT Rating Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Output Current Value -1.0 to 3.6 -1.0 to 3.6 -1.0 to 3.6 -40 to 85 -55 to 150 0.6 50 Unit V V V C C W mA
Note: ESD Immunity: Spansion Flash memory Multi-Chip Products (MCPs) may contain component devices that are developed by Spansion and component devices that are developed by a third party (third-party components). Spansion components are tested and guaranteed to the ESD immunity levels listed in the corresponding Spansion Flash memory Qualification Database. Third-party components are neither tested nor guaranteed by Spansion for ESD immunity. However, ESD test results for third-party components may be available from the component manufacturer. Component manufacturer contact information is listed in the Spansion MCP Qualification Report, when available. The Spansion Flash memory Qualification Database and Spansion MCP Qualification Report are available from AMD and Fujitsu sales offices.
DC Recommended Operating Conditions (Ta = -40C to 85C)
Symbol VDD VIH VIL Parameter Power Supply Voltage Input High Voltage Input Low Voltage Min 2.6 2.0 -0.3 (Note) Typ 2.75 -- -- Max 3.3 VDD + 0.3 (Note) 0.4 V Unit
Note: VIH (Max) VDD = 1.0 V with 10 ns pulse width. VIL (Min) -1.0 V with 10 ns pulse width.
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Preliminary
DC Characteristics (Ta = -40C to 85C, VDD = 2.6 to 3.3 V) (See Note 3 to 4)
Symbol IIL ILO VOH VOL IDDO1 IDDO2 IDDS IDDSD Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Operating Current Page Access Operating Current Standby Current(MOS) Deep Power-down Standby Current VIN = 0 V to VDD Output disable, VOUT = 0 V to VDD IOH = - 0.5 mA IOL = 1.0 mA CE1#= VIL, CE2 = VIH, IOUT = 0 mA, tRC = min ET5UZ8A-43DS ET5VB5A-43DS Test Condition Min -1.0 -1.0 2.0 -- -- -- -- -- -- -- Typ. -- -- 3/4 -- -- -- -- -- -- -- Max +1.0 +1.0 V 0.4 40 50 25 70 100 5 Unit A A V V mA mA mA A A
CE1#= VIL, CE2 = VIH, IOUT = 0 mA Page add. cycling, tRC = min CE1# = VDD - 0.2 V, CE2 = VDD - 0.2 V CE2 = 0.2 V ET5UZ8A-43DS ET5VB5A-43DS
Capacitance (Ta = 25C, f = 1 MHz)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = GND VOUT = GND Max 10 10 Unit pF pF
Note: This parameter is sampled periodically and is not 100% tested.
AC Characteristics and Operating Conditions
(Ta = -40C to 85C, VDD = 2.6 to 3.3 V) (See Note 5 to 11)
Symbol tRC tACC tCO tOE tBA tCOE tOEE tBE tOD tODO tBD Read Cycle Time Address Access Time Chip Enable (CE1#) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Data Byte Control High to Output High-Z Parameter Min 70 -- -- -- -- 10 0 0 -- -- -- Max 10000 70 70 25 25 -- -- -- 20 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns
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Preliminary
Symbol tOH tPM tPC tAA tAOH tWC tWP tCW tBW tAW tAS tWR tCEH tWEH tODW tOEW tDS tDH tCS tCH tDPD tCHC tCHP Output Data Hold Time Page Mode Time Page Mode Cycle Time
Parameter
Min 10 70 30 -- 10 70 50 70 60 60 0 0 10 6 -- 0 30 0 0 300 10 0 30
Max -- 10000 -- 30 -- 10000 -- -- -- -- -- -- -- -- 20
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Page Mode Address Access Time Page Mode Output Data Hold Time Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Byte Control to End of Write Address Valid to End of Write Address Set-up Time Write Recovery Time Chip Enable High Pulse Width Write Enable High Pulse Width WE# Low to Output High-Z WE# High to Output Active Data Set-up Time Data Hold Time CE2 Set-up Time CE2 Hold Time CE2 Pulse Width CE2 Hold from CE1# CE2 Hold from Power On
-- -- -- -- -- -- --
ns ns ns s ms ns s
AC Test Conditions
Parameter Output load Input pulse level Timing measurements Reference level tR, tF Condition 30 pF + 1 TTL Gate VDD - 0.2 V, 0.2 V VDD x 0.5 VDD x 0.5 5 ns
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Preliminary
Timing Diagrams
Read Timings
tRC Address A0 toA20(32M) A0 to A21(64M)
tACC
tCO
tOH
CE1#
CE2 tOE OE# tODO
WE#
Fix-H tOD
tBA , UB# LB# tBE DOUT I/O1 to O16 I/ tOEE Hi-Z tCOE INDETERMI NATE VALID DA OUT TA Hi-Z tBD
Figure 1. Read Cycle
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Preliminary
tPM Address A0 toA2 Address A3 toA20(32M) A3 toA21(64M)
CE1#
tRC
tPC
tPC
tPC
CE2
OE#
Fix-H
WE#
UB# LB# , tBA DOUT I/O1 to I/O1 6 tOE tOEE DOUT tAA tAOH DOUT tAA tAOH DOUT tAOH tBD tOH DOUT Hi-Z tOD
tBE Hi-Z
tACC
tCOE tCO
tAA tODO * Maximum words 8
Figure 2.
Page Read Cycle (8 Words Access)
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Preliminary
Write Timings
tWC Address A0 toA20(32M) A0 toA21(64M) tAS
WE#
tAW tWP tWR
tWEH
tCW
CE1#
tWR
tCH CE2 tBW , UB# LB# tODW DOUT I/O1 to I/O1 6 DIN I/O1 to I/O1 6 (See Note ) 9 (See Note 10) Hi-Z tDS tDH (See Note ) 9 tOEW (See Note 11) tWR
VALID DA IN TA
Figure 3. Write Cycle #1 (WE# Controlled) (See Note 8)
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Preliminary
tWC Address A0 toA20(32M) A0 toA21(64M) tAS
WE#
tAW tWP tWR
tCEH tCW
CE1#
tWR
tCH CE2 tBW UB# LB# , tBE DOUT I/O1 to I/O1 6 Hi-Z tCOE tDS DIN I/O1 to I/O1 6 (See Note ) 9 tDH tODW Hi-Z tWR
VALID DA IN TA
Figure 4.
Write Cycle #2 (CE# Controlled) (See Note 8)
Deep Power-down Timing
CE1#
tDPD CE2 tCS tCH
Figure 5.
Deep Power Down Timing
Power-on Timing
VDD VDD min
CE1#
tCHC
CE2 tCHP
tCH
Figure 6. Power-on Timing
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Preliminary
Provisions of Address Skew
Read
In case multiple invalid address cycles shorter than tRC min sustain over 10 s in an active status, at least one valid address cycle over tRC min is required during 10s.
over 10 s m
CE1#
WE#
Address tRC min
Figure 7. Write
Read
In case multiple invalid address cycles shorter than tWC min sustain over 10 s in an active status, at least one valid address cycle over tWC min is required during 10 s.
CE1#
tWPmin
WE#
Address tWCmin
Figure 8. Write
Notes:
1. Stresses greater than listed under "Absolute Maximum Ratings" section may cause permanent damage to the device. 2. All voltages are reference to GND. 3. IDDO depends on the cycle time. 4. IDDO depends on output loading. Specified values are defined with the output open condition. 5. AC measurements are assumed tR, tF = 5 ns. 6. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not output voltage reference levels. 7. Data cannot be retained at deep power-down stand-by mode. 8. If OE# is high during the write cycle, the outputs will remain at high impedance. 9. During the output state of I/O signals, input signals of reverse polarity must not be applied. 10. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance. 11. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance.
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Preliminary
Revision Summary
Revision A0 (November 9, 2004)
Initial Release
Revision A1 (January 6, 2005)
Global Changed text designations from Flash to PL127J. Pin Connection Changed Pinout reference. Block Diagram Changed pin names on a couple pins. Changed device designations from Flash to PL127J. S29GLxxxN_MCP section Added updated version to this section.
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Prelimiary
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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S75PL127J MCPs
S75PL127J_00A0 January 6, 2005

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